Subversion Repositories amber

# ----------------------------------------------------------------
#                                                               //
#   Xilinx Spartan-6 FPGA synthesis Verilog source file list    //
#                                                               //
#   This file is part of the Amber project                      //
#   http://www.opencores.org/project,amber                      //
#                                                               //
#   Description                                                 //
#                                                               //
#   Author(s):                                                  //
#       - Conor Santifort, csantifort.amber@gmail.com           //
#                                                               //
#/ ///////////////////////////////////////////////////////////////
#                                                               //
#  Copyright (C) 2010 Authors and OPENCORES.ORG                 //
#                                                               //
#  This source file may be used and distributed without         //
#  restriction provided that this copyright statement is not    //
#  removed from the file and that any derivative work contains  //
#  the original copyright notice and the associated disclaimer. //
#                                                               //
#  This source file is free software; you can redistribute it   //
#  and/or modify it under the terms of the GNU Lesser General   //
#  Public License as published by the Free Software Foundation; //
#  either version 2.1 of the License, or (at your option) any   //
#  later version.                                               //
#                                                               //
#  This source is distributed in the hope that it will be       //
#  useful, but WITHOUT ANY WARRANTY; without even the implied   //
#  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
#  PURPOSE.  See the GNU Lesser General Public License for more //
#  details.                                                     //
#                                                               //
#  You should have received a copy of the GNU Lesser General    //
#  Public License along with this source; if not, download it   //
#  from http://www.opencores.org/lgpl.shtml                     //
#                                                               //
# ----------------------------------------------------------------

# System
verilog work ../../vlog/system/boot_mem.v
verilog work ../../vlog/system/clocks_resets.v
verilog work ../../vlog/system/interrupt_controller.v
verilog work ../../vlog/system/system.v
verilog work ../../vlog/system/test_module.v
verilog work ../../vlog/system/timer_module.v
verilog work ../../vlog/system/uart.v
verilog work ../../vlog/system/wb_xs6_ddr3_bridge.v
verilog work ../../vlog/system/wb_xv6_ddr3_bridge.v
verilog work ../../vlog/system/wishbone_arbiter.v
verilog work ../../vlog/system/afifo.v
verilog work ../../vlog/system/ddr3_afifo.v

# EthMac
verilog work ../../vlog/ethmac/eth_clockgen.v
verilog work ../../vlog/ethmac/eth_crc.v
verilog work ../../vlog/ethmac/eth_fifo.v
verilog work ../../vlog/ethmac/eth_maccontrol.v
verilog work ../../vlog/ethmac/eth_macstatus.v
verilog work ../../vlog/ethmac/eth_miim.v
verilog work ../../vlog/ethmac/eth_outputcontrol.v
verilog work ../../vlog/ethmac/eth_random.v
verilog work ../../vlog/ethmac/eth_receivecontrol.v
verilog work ../../vlog/ethmac/eth_registers.v
verilog work ../../vlog/ethmac/eth_register.v
verilog work ../../vlog/ethmac/eth_rxaddrcheck.v
verilog work ../../vlog/ethmac/eth_rxcounters.v
verilog work ../../vlog/ethmac/eth_rxethmac.v
verilog work ../../vlog/ethmac/eth_rxstatem.v
verilog work ../../vlog/ethmac/eth_shiftreg.v
verilog work ../../vlog/ethmac/eth_spram_256x32.v
verilog work ../../vlog/ethmac/eth_top.v
verilog work ../../vlog/ethmac/eth_transmitcontrol.v
verilog work ../../vlog/ethmac/eth_txcounters.v
verilog work ../../vlog/ethmac/eth_txethmac.v
verilog work ../../vlog/ethmac/eth_txstatem.v
verilog work ../../vlog/ethmac/eth_wishbone.v
verilog work ../../vlog/ethmac/xilinx_dist_ram_16x32.v

# Amber 23
verilog work ../../vlog/amber23/a23_alu.v
verilog work ../../vlog/amber23/a23_barrel_shift.v
verilog work ../../vlog/amber23/a23_cache.v
verilog work ../../vlog/amber23/a23_coprocessor.v
verilog work ../../vlog/amber23/a23_core.v
verilog work ../../vlog/amber23/a23_decode.v
verilog work ../../vlog/amber23/a23_execute.v
verilog work ../../vlog/amber23/a23_fetch.v
verilog work ../../vlog/amber23/a23_multiply.v
verilog work ../../vlog/amber23/a23_register_bank.v
verilog work ../../vlog/amber23/a23_wishbone.v

# Amber 25
verilog work ../../vlog/amber25/a25_alu.v
verilog work ../../vlog/amber25/a25_barrel_shift.v
verilog work ../../vlog/amber25/a25_coprocessor.v
verilog work ../../vlog/amber25/a25_core.v
verilog work ../../vlog/amber25/a25_dcache.v
verilog work ../../vlog/amber25/a25_decode.v
verilog work ../../vlog/amber25/a25_execute.v
verilog work ../../vlog/amber25/a25_fetch.v
verilog work ../../vlog/amber25/a25_icache.v
verilog work ../../vlog/amber25/a25_mem.v
verilog work ../../vlog/amber25/a25_multiply.v
verilog work ../../vlog/amber25/a25_register_bank.v
verilog work ../../vlog/amber25/a25_wishbone.v
verilog work ../../vlog/amber25/a25_write_back.v

# Xilinx Spartan-6 FPGA Hardware wrappers
verilog work ../../vlog/lib/xs6_addsub_n.v
verilog work ../../vlog/lib/xs6_sram_2048x32_byte_en.v
verilog work ../../vlog/lib/xs6_sram_256x128_byte_en.v
verilog work ../../vlog/lib/xs6_sram_256x21_line_en.v
verilog work ../../vlog/lib/xs6_sram_256x32_byte_en.v

# Xilinx Spartan-6 DDR3 I/F
verilog work ../../vlog/xs6_ddr3/mcb_ddr3.v
verilog work ../../vlog/xs6_ddr3/iodrp_controller.v
verilog work ../../vlog/xs6_ddr3/iodrp_mcb_controller.v
verilog work ../../vlog/xs6_ddr3/mcb_raw_wrapper.v
verilog work ../../vlog/xs6_ddr3/mcb_soft_calibration_top.v
verilog work ../../vlog/xs6_ddr3/mcb_soft_calibration.v
verilog work ../../vlog/xs6_ddr3/memc3_infrastructure.v
verilog work ../../vlog/xs6_ddr3/memc3_wrapper.v