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[/] [amber/] [trunk/] [hw/] [tests/] [cache_flush.S] - Rev 10
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/*****************************************************************// //// Amber 2 Core Instruction Test //// //// This file is part of the Amber project //// http://www.opencores.org/project,amber //// //// Description //// Tests the cache flush function. Does a flush in the middle //// of a sequence of data reads. Checks that all the data //// reads are correct. //// //// Author(s): //// - Conor Santifort, csantifort.amber@gmail.com //// ////////////////////////////////////////////////////////////////////// //// Copyright (C) 2010 Authors and OPENCORES.ORG //// //// This source file may be used and distributed without //// restriction provided that this copyright statement is not //// removed from the file and that any derivative work contains //// the original copyright notice and the associated disclaimer. //// //// This source file is free software; you can redistribute it //// and/or modify it under the terms of the GNU Lesser General //// Public License as published by the Free Software Foundation; //// either version 2.1 of the License, or (at your option) any //// later version. //// //// This source is distributed in the hope that it will be //// useful, but WITHOUT ANY WARRANTY; without even the implied //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// PURPOSE. See the GNU Lesser General Public License for more //// details. //// //// You should have received a copy of the GNU Lesser General //// Public License along with this source; if not, download it //// from http://www.opencores.org/lgpl.shtml //// //*****************************************************************/#include "amber_registers.h".section .text.globl mainmain:@ ---------------------@ Enable the cache@ ---------------------mov r0, #0x00000001mcr p15, 0, r0, c3, c0, 0 @ cacheable areamov r0, #1mcr p15, 0, r0, c2, c0, 0 @ cache enablenopnop@ Write to a block of memory that straddles@ across a cache region boundary so that@ the first 16 bytes are cacheable and@ the second 16 are notldr r0, AdrTestBasemov r2, #0x201: subs r2, r2, #1str r2, [r0], #4bne 1b@ loop a few times so that@ the instructions will be caches on the second and@ subsequent passesmov r7, #7@ Read back the same blockloop: ldr r3, AdrTestBasemov r5, #0x20mov r6, #02: ldr r4, [r3], #4add r6, r6, r4@ Flush the cache when the r7 loop count value is even@ a write of any value to cp15, reg 1 will trigger a flushands r8, r7, #1cmpeq r5, #21cmpne r5, #0x100mcreq p15, 0, r0, c1, c0, 0 @ cache enablesubs r5, r5, #1bne 2b@ Check that the sum of the data reads is correctcmp r6, #0x1f0movne r10, #10bne testfailsubs r7, r7, #1bne loopb testpass@ ------------------------------------------@ ------------------------------------------testfail:ldr r11, AdrTestStatusstr r10, [r11]b testfailtestpass:ldr r11, AdrTestStatusmov r10, #17str r10, [r11]b testpass/* Write 17 to this address to generate a Test Passed message */AdrTestStatus: .word ADR_AMBER_TEST_STATUSAdrTestBase : .word 0x001fffc0/* sum of numbers 0 to 2047 inclusive */MagicNumber1024 : .word 523776MagicNumber2048 : .word 2096128/* ========================================================================= *//* ========================================================================= */
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