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[/] [amber/] [trunk/] [hw/] [tests/] [ddr31.S] - Rev 65
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/*****************************************************************// //// Amber 2 Core DDR3 Memory Access //// //// This file is part of the Amber project //// http://www.opencores.org/project,amber //// //// Description //// Word accesses to random addresses in DDR3 memory //// The test creates a list of addresses in an area of //// boot_mem. It then writes to all addresses with data value //// equal to address. Finally it reads back all locations //// checking that the read value is correct. //// //// Author(s): //// - Conor Santifort, csantifort.amber@gmail.com //// ////////////////////////////////////////////////////////////////////// //// Copyright (C) 2010 Authors and OPENCORES.ORG //// //// This source file may be used and distributed without //// restriction provided that this copyright statement is not //// removed from the file and that any derivative work contains //// the original copyright notice and the associated disclaimer. //// //// This source file is free software; you can redistribute it //// and/or modify it under the terms of the GNU Lesser General //// Public License as published by the Free Software Foundation; //// either version 2.1 of the License, or (at your option) any //// later version. //// //// This source is distributed in the hope that it will be //// useful, but WITHOUT ANY WARRANTY; without even the implied //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// PURPOSE. See the GNU Lesser General Public License for more //// details. //// //// You should have received a copy of the GNU Lesser General //// Public License along with this source; if not, download it //// from http://www.opencores.org/lgpl.shtml //// //*****************************************************************/#include "amber_registers.h"#define ARRAY_WORDS 0x40.section .text.globl mainmain:@ --------------------------------------------@ Quick Pre-Testldr r0, DDRBaseadd r4, r0, #12mov r1, #0xffmov r3, #0x55str r1, [r0]str r3, [r4]ldr r2, [r0]ldr r5, [r4]cmp r1, r2movne r10, #10bne testfailcmp r3, r5movne r10, #15bne testfail@ --------------------------------------------@ Create an array of random accresses@ Write data = address to each address@ Read back and verify data is correct@ setupldr r0, AdrRanNumldr r9, PointerBaseldr r10, DDRBasemov r11, #ARRAY_WORDS1: ldmia r0,{r1-r8}add r1, r10, r1, lsl #2add r2, r1, r2, lsl #2add r3, r2, r3, lsl #2add r4, r3, r4, lsl #2add r5, r4, r5, lsl #2add r6, r5, r6, lsl #2add r7, r6, r7, lsl #2add r8, r7, r8, lsl #2stmia r9,{r1-r8}add r9, r9, #32mov r10, r8subs r11, r11, #1bne 1b@ --------------------------------------------@ Write array to ddr memoryldr r9, PointerBasemov r11, #ARRAY_WORDS2: ldmia r9, {r1-r8}str r1, [r1]str r2, [r2]str r3, [r3]str r4, [r4]str r5, [r5]str r6, [r6]str r7, [r7]str r8, [r8]add r9, r9, #32subs r11, r11, #1bne 2b@ --------------------------------------------@ Read array back from ddr and verify itldr r9, PointerBasemov r11, #ARRAY_WORDS3: ldmia r9, {r1-r8}@ r1ldr r12, [r1]cmp r12, r1movne r10, #10bne testfail@ r2ldr r12, [r2]cmp r12, r2movne r10, #10bne testfail@ r3ldr r12, [r3]cmp r12, r3movne r10, #10bne testfail@ r4ldr r12, [r4]cmp r12, r4movne r10, #10bne testfail@ r5ldr r12, [r5]cmp r12, r5movne r10, #10bne testfail@ r6ldr r12, [r6]cmp r12, r6movne r10, #10bne testfail@ r7ldr r12, [r7]cmp r12, r7movne r10, #10bne testfail@ r8ldr r12, [r8]cmp r12, r8movne r10, #10bne testfailadd r9, r9, #32subs r11, r11, #1bne 3bb testpasstestfail:ldr r11, AdrTestStatusstr r10, [r11]b testfailtestpass:ldr r11, AdrTestStatusmov r10, #17str r10, [r11]b testpass/* Write 17 to this address to generate a Test Passed message */AdrTestStatus: .word ADR_AMBER_TEST_STATUSAdrRanNum: .word ADR_AMBER_TEST_RANDOM_NUMPointerBase: .word 0x1000DDRBase: .word 0x20000
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