URL
https://opencores.org/ocsvn/amber/amber/trunk
Subversion Repositories amber
[/] [amber/] [trunk/] [hw/] [tests/] [firq.S] - Rev 80
Go to most recent revision | Compare with Previous | Blame | View Log
/*****************************************************************// //// Amber 2 Core Interrupt Test //// //// This file is part of the Amber project //// http://www.opencores.org/project,amber //// //// Description //// Tests Fast Interrupt //// Executes 20 FIRQs randomly while executing a small loop //// of code. Test checks the full set of FIRQ registers (r8 to //// r14) and will only pass if all interrupts are handled //// correctly //// //// Author(s): //// - Conor Santifort, csantifort.amber@gmail.com //// ////////////////////////////////////////////////////////////////////// //// Copyright (C) 2010 Authors and OPENCORES.ORG //// //// This source file may be used and distributed without //// restriction provided that this copyright statement is not //// removed from the file and that any derivative work contains //// the original copyright notice and the associated disclaimer. //// //// This source file is free software; you can redistribute it //// and/or modify it under the terms of the GNU Lesser General //// Public License as published by the Free Software Foundation; //// either version 2.1 of the License, or (at your option) any //// later version. //// //// This source is distributed in the hope that it will be //// useful, but WITHOUT ANY WARRANTY; without even the implied //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// PURPOSE. See the GNU Lesser General Public License for more //// details. //// //// You should have received a copy of the GNU Lesser General //// Public License along with this source; if not, download it //// from http://www.opencores.org/lgpl.shtml //// //*****************************************************************/#include "amber_registers.h".section .text.globl mainmain:@ ---------------------@ Interrupt Vector Table@ ---------------------/* 0x00 Reset Interrupt vector address */b start/* 0x04 Undefined Instruction Interrupt vector address */b testfail/* 0x08 SWI Interrupt vector address */b testfail/* 0x0c Prefetch abort Interrupt vector address */b testfail/* 0x10 Data abort Interrupt vector address */b testfailb testfail/* 0x18 IRQ vector address */b testfail/* 0x1c FIRQ vector address */b service_firqstart:/* Switch to User Mode *//* and unset interrupt mask bits */mov r0, #0x00000000teqp pc, r0@ Check that we're in user mode nowmov r2, pcands r2, r2, #3movne r10, #10bne testfail@ Set upmov r1, #0mov r3, #20 @ Number of times to run the outer loop of the test@ set the firq timer to trigger a firq requestmloop:ldr r4, AdrRanNumldr r5, [r4]and r5, r5, #0x3fadd r5, r5, #15ldr r6, AdrFIRQTimerstr r5, [r6]@ loop foreverloop: mov r8, #0x17mov r9, #0x39mov r10, #0x87mov r11, #0x14mov r12, #0x97mov r13, #0x52mov r7, #0add r7, r8, r7add r7, r9, r7add r7, r10, r7add r7, r11, r7add r7, r12, r7add r7, r13, r7@ only jump to check regs after an interrupt has occurred.@ The interrupt service routine sets r1 to a 1@ and the check_regs sequence sets it back to 0cmp r1, #1beq check_regsb loopnoploop1: @ This lable needs to be 1 instruction after the end of the@ loop. The interrupt lr address is current instruction address + 4@ so if the interrupt hits on the b loop, then the FIRQ lr will@ be 2 instructions after the end of the loopservice_firq:@ Now in FIRQ mode@ Turn off the FIRQ interrupt count down trigger by writing a zero to itldr r10, AdrFIRQTimermov r11, #0str r11, [r10]@ Check that the FIRQ Link Register (r14) got the correct return address@ Don't know exactly when the interrupt occurred so check the range loop to loop1ldr r2, Adrloopldr r13, PCMaskand r13, lr, r13cmp r13, r2movlt r10, #100blt testfailldr r2, Adrloop1cmp r13, r2movgt r10, #110bgt testfail@ save a 1 to r1, this will exit the loop to testpassmov r1, #1mov r8, #0x10mov r9, #0x20mov r10, #0x30mov r11, #0x40mov r12, #0x50mov r13, #0x60@ Jump straight back to normal execution, returning to user modesubs pc, r14, #4check_regs:mov r1, #0ldr r6, Sumcmp r7, r6movne r10, #15bne testfailcmp r8, #0x17movne r10, #20bne testfailcmp r9, #0x39movne r10, #30bne testfailcmp r10, #0x87movne r10, #40bne testfailcmp r11, #0x14movne r10, #50bne testfailcmp r12, #0x97movne r10, #60bne testfailcmp r13, #0x52movne r10, #70bne testfailcmp r3, #0beq testpasssub r3, r3, #1b mloop@ ------------------------------------------@ ------------------------------------------testfail:ldr r11, AdrTestStatusstr r10, [r11]b testfailtestpass:ldr r11, AdrTestStatusmov r10, #17str r10, [r11]b testpass@ ------------------------------------------@ ------------------------------------------AdrTestStatus: .word ADR_AMBER_TEST_STATUSAdrRanNum: .word ADR_AMBER_TEST_RANDOM_NUMAdrFIRQTimer: .word ADR_AMBER_TEST_FIRQ_TIMERAdrloop: .word loopAdrloop1: .word loop1Sum: .word 0x1d4PCMask: .word 0x03fffffc
Go to most recent revision | Compare with Previous | Blame | View Log