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[/] [amber/] [trunk/] [hw/] [tests/] [flow2.S] - Rev 49
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/*****************************************************************// //// Amber 2 Core Instruction Test //// //// This file is part of the Amber project //// http://www.opencores.org/project,amber //// //// Description //// Tests instruction and data flow. //// Specifically tests that a stream of str instrutions writing //// to cached memory works correctly. //// //// Author(s): //// - Conor Santifort, csantifort.amber@gmail.com //// ////////////////////////////////////////////////////////////////////// //// Copyright (C) 2010 Authors and OPENCORES.ORG //// //// This source file may be used and distributed without //// restriction provided that this copyright statement is not //// removed from the file and that any derivative work contains //// the original copyright notice and the associated disclaimer. //// //// This source file is free software; you can redistribute it //// and/or modify it under the terms of the GNU Lesser General //// Public License as published by the Free Software Foundation; //// either version 2.1 of the License, or (at your option) any //// later version. //// //// This source is distributed in the hope that it will be //// useful, but WITHOUT ANY WARRANTY; without even the implied //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// PURPOSE. See the GNU Lesser General Public License for more //// details. //// //// You should have received a copy of the GNU Lesser General //// Public License along with this source; if not, download it //// from http://www.opencores.org/lgpl.shtml //// //*****************************************************************/#include "amber_registers.h".section .text.globl mainmain:@ Run through the test 4 times@ 1 - cache off@ 2 - cache on but empty@ 3 - cache on and loaded@ 4 - same as 3mov r10, #401: mov r0, #0x1000ldr r1, Data2str r1, [r0]ldr r2, [r0], #1ldr r3, [r0], #1ldr r4, [r0], #1ldr r5, [r0]ldrb r6, [r0], #-1ldrb r7, [r0], #-1ldrb r8, [r0], #-1ldrb r9, [r0]cmp r2, r1addne r10, r10, #2bne testfailmov r1, r1, ror #8cmp r3, r1addne r10, r10, #3bne testfailmov r1, r1, ror #8cmp r4, r1addne r10, r10, #4bne testfailmov r1, r1, ror #8cmp r5, r1addne r10, r10, #5bne testfail@ Test conflict detectionmov r1, #5ldr r1, Data1mov r2, r1cmp r2, #3addne r10, r10, #6bne testfail@ Test ldm/stm with conflictsmov r13, #0x1000orr r13, r13, #0x08ldr r0, =Data1ldmia r0, {r1-r5}mov r6, r13str r1, [r6], #4str r2, [r6], #4str r3, [r6], #4str r4, [r6], #4str r5, [r6], #4mov r6, r13ldr r7, [r6], #4ldr r8, [r6], #4ldr r9, [r6], #4ldr r14, [r6], #4ldr r11, [r6], #4cmp r1, r7cmpeq r2, r8cmpeq r3, r9cmpeq r4, r14cmpeq r5, r11addne r10, r10, #7bne testfail@ Test conflict detection for a stmmov r6, r13mov r2, #3mov r0, #4ldr r1, Data3stm r6, {r0,r1,r2}mov r6, r13ldr r4, [r6, #4]cmp r1, r4addne r10, r10, #8bne testfail@ Test conflict detection for addldr r5, Data1add r5, r5, #1cmp r5, #4addne r10, r10, #9bne testfail@ Throw in an uncached memory accessmov r1, #0x99ldr r0, AdrHiBootBasestr r1, [r0]ldr r2, [r0]cmp r2, #0x99addne r10, r10, #100bne testfail@ ---------------------@ Enable the cache@ ---------------------mvn r0, #0mcr 15, 0, r0, cr3, cr0, 0 @ cacheable areamov r0, #1mcr 15, 0, r0, cr2, cr0, 0 @ cache enablesubs r10, r10, #10bne 1bb testpasstestfail:ldr r11, AdrTestStatusstr r10, [r11]b testfailtestpass:ldr r11, AdrTestStatusmov r10, #17str r10, [r11]b testpass/* Write 17 to this address to generate a Test Passed message */AdrTestStatus: .word ADR_AMBER_TEST_STATUSAdrHiBootBase: .word ADR_HIBOOT_BASEData1: .word 0x3.word 0x4.word 0x5.word 0x6.word 0x7Data2: .word 0x44332211Data3: .word 0x12345678/* ========================================================================= *//* ========================================================================= */
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