URL
https://opencores.org/ocsvn/amber/amber/trunk
Subversion Repositories amber
[/] [amber/] [trunk/] [hw/] [tests/] [ldm_stm_onetwo.S] - Rev 49
Go to most recent revision | Compare with Previous | Blame | View Log
/*****************************************************************// //// Amber 2 Core Instruction Test //// //// This file is part of the Amber project //// http://www.opencores.org/project,amber //// //// Description //// Tests ldm and stm of single registers with cache enabled. //// Tests ldm and stm of 2 registers with cache enabled. //// //// Author(s): //// - Conor Santifort, csantifort.amber@gmail.com //// ////////////////////////////////////////////////////////////////////// //// Copyright (C) 2010 Authors and OPENCORES.ORG //// //// This source file may be used and distributed without //// restriction provided that this copyright statement is not //// removed from the file and that any derivative work contains //// the original copyright notice and the associated disclaimer. //// //// This source file is free software; you can redistribute it //// and/or modify it under the terms of the GNU Lesser General //// Public License as published by the Free Software Foundation; //// either version 2.1 of the License, or (at your option) any //// later version. //// //// This source is distributed in the hope that it will be //// useful, but WITHOUT ANY WARRANTY; without even the implied //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// PURPOSE. See the GNU Lesser General Public License for more //// details. //// //// You should have received a copy of the GNU Lesser General //// Public License along with this source; if not, download it //// from http://www.opencores.org/lgpl.shtml //// //*****************************************************************/#include "amber_registers.h".section .text.globl mainmain:@ Run through the test 4 times@ 1 - cache off@ 2 - cache on but empty@ 3 - cache on and loaded@ 4 - same as 3mov r10, #400@ stm 1 -------------------------------------1: mov r0, #0x1000mov r1, r0ldr r2, Data2stmia r1!, {r2}ldr r3, [r0], #4@ Check that the address pointers were both incremented correctlycmp r0, r1addne r10, r10, #1bne testfail@ Check that the correct value was saved to memorycmp r2, r3addne r10, r10, #2bne testfail@ ldm 1 -------------------------------------mov r0, #0x1000mov r1, r0ldr r2, Data2str r2, [r1], #4ldmia r0!, {r3}@ Check that the address pointers were both incremented correctlycmp r0, r1addne r10, r10, #3bne testfail@ Check that the correct value was saved to memorycmp r2, r3addne r10, r10, #4bne testfail@ ldm 1, pc -------------------------------------mov r0, #0x1000mov r1, r0ldr r2, =jpc1str r2, [r1], #4ldmia r0!, {pc}b testfailb testfailb testfailb testfailjpc1: b 2fb testfailb testfailb testfailb testfail@ Check that the address pointers were both incremented correctly2: cmp r0, r1addne r10, r10, #5bne testfail@ stm 2 -------------------------------------mov r0, #0x1000mov r1, r0mov r4, #0x33mov r6, #0x44stmia r1!, {r4, r6}ldr r7, [r0], #4ldr r8, [r0], #4@ Check that the address pointers were both incremented correctlycmp r0, r1addne r10, r10, #6bne testfail@ Check that the correct value was saved to memorycmp r4, r7addne r10, r10, #7bne testfailcmp r6, r8addne r10, r10, #8bne testfail@ ldm 2 -------------------------------------mov r0, #0x1000mov r1, r0mov r4, #0x33mov r5, #0x44str r4, [r0], #4str r5, [r0], #4ldmia r1!, {r6, r7}@ Check that the address pointers were both incremented correctlycmp r0, r1addne r10, r10, #9bne testfail@ Check that the correct value was saved to memorycmp r4, r6addne r10, r10, #10bne testfailcmp r5, r7addne r10, r10, #11bne testfail@ ldm 2, pc -------------------------------------mov r0, #0x1000mov r1, r0mov r4, #0x33ldr r5, =jpc2str r4, [r0], #4str r5, [r0], #4ldmia r1!, {r6, pc}b testfailb testfailb testfailb testfailb testfailjpc2: b 2fb testfailb testfailb testfailb testfailb testfail@ Check that the address pointers were both incremented correctly2: cmp r0, r1addne r10, r10, #12bne testfail@ ---------------------@ Enable the cache@ ---------------------mvn r13, #0mcr 15, 0, r13, cr3, cr13, 0 @ cacheable areamov r13, #1mcr 15, 0, r13, cr2, cr13, 0 @ cache enablesubs r10, r10, #100bne 1bb testpasstestfail:ldr r11, AdrTestStatusstr r10, [r11]b testfailtestpass:ldr r11, AdrTestStatusmov r10, #17str r10, [r11]b testpass/* Write 17 to this address to generate a Test Passed message */AdrTestStatus: .word ADR_AMBER_TEST_STATUSAdrHiBootBase: .word ADR_HIBOOT_BASEData1: .word 0x3.word 0x4.word 0x5.word 0x6.word 0x7Data2: .word 0x44332211Data3: .word 0x12345678/* ========================================================================= *//* ========================================================================= */
Go to most recent revision | Compare with Previous | Blame | View Log