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[/] [amber/] [trunk/] [hw/] [tests/] [stm2.S] - Rev 32
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/*****************************************************************// //// Amber 2 Core Instruction Test //// //// This file is part of the Amber project //// http://www.opencores.org/project,amber //// //// Description //// Test jumps into user mode, loads some values into //// registers r8 - r14, then jumps to FIRQ and //// saves the user mode registers to memory //// //// Author(s): //// - Conor Santifort, csantifort.amber@gmail.com //// ////////////////////////////////////////////////////////////////////// //// Copyright (C) 2010 Authors and OPENCORES.ORG //// //// This source file may be used and distributed without //// restriction provided that this copyright statement is not //// removed from the file and that any derivative work contains //// the original copyright notice and the associated disclaimer. //// //// This source file is free software; you can redistribute it //// and/or modify it under the terms of the GNU Lesser General //// Public License as published by the Free Software Foundation; //// either version 2.1 of the License, or (at your option) any //// later version. //// //// This source is distributed in the hope that it will be //// useful, but WITHOUT ANY WARRANTY; without even the implied //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// PURPOSE. See the GNU Lesser General Public License for more //// details. //// //// You should have received a copy of the GNU Lesser General //// Public License along with this source; if not, download it //// from http://www.opencores.org/lgpl.shtml //// //*****************************************************************/#include "amber_registers.h".section .text.globl mainmain:/* 0x00 Reset Interrupt vector address */b start/* 0x04 Undefined Instruction Interrupt vector address */b testfail/* 0x08 SWI Interrupt vector address */b testfail/* 0x0c Prefetch abort Interrupt vector address */b testfail/* 0x10 Data abort Interrupt vector address */b testfail/* Address exception Interrupt vector address */b testfail/* 0x18 IRQ vector address */b testfail/* 0x1c FIRQ vector address */b service_firqstart:@ Jump into user modemov r2, #0x00000010teqp pc, r2ldr r3, StaticBaseldmia r3, {r8-r14}@ Jumo into FIRQ mode by triggering a Fast Interrupt@ set the firq timer to trigger a firq requestldr r5, AdrFIRQTimermov r6, #10str r6, [r5]@ loop waiting for the interrupt@ to triggerloop: nopnopnopb loop@ These should never get executedb testfailb testfailb testfail@ ------------------------------------------@ ------------------------------------------service_firq:@ Disable the FIRQ Timerldr r10, AdrFIRQTimermov r11, #0str r11, [r10]@ load a couple of numbers@ into FIRQ registersmov r9, #50mov r10, #60mov r11, #70mov r12, #80mov r13, #90mov r14, #100movs r1, #0ldr r2, StoreBase@ execute the stm instruction@ and check that its conditional execution works@ Now in firq mode but this instruction saves the@ user mode register valuesstmeqia r2, {r8-pc}^mov r4, #4ldr r3, [r2], #4cmp r3, #8movne r10, #20bne testfailldr r3, [r2], #4cmp r3, #9movne r10, #30bne testfailldr r3, [r2], #4cmp r3, #10movne r10, #40bne testfailldr r3, [r2], #4cmp r3, #11movne r10, #50bne testfailldr r3, [r2], #4cmp r3, #12movne r10, #60bne testfailldr r3, [r2], #4cmp r3, #13movne r10, #70bne testfailldr r3, [r2], #4cmp r3, #14movne r10, #80bne testfailb testpasstestfail:ldr r11, AdrTestStatusstr r10, [r11]b testfailtestpass:ldr r11, AdrTestStatusmov r10, #17str r10, [r11]b testpass/* Write 17 to this address to generate a Test Passed message */AdrTestStatus: .word ADR_AMBER_TEST_STATUSAdrFIRQTimer: .word ADR_AMBER_TEST_FIRQ_TIMERStoreBase: .word 0x800StaticBase: .word Data1StaticEnd: .word Data18Data1: .word 0x08.word 0x09.word 0x0a.word 0x0b.word 0x0c.word 0x0d.word 0x0e.word 0x0f.word 0x10Data18: .word 0x11/* ========================================================================= *//* ========================================================================= */
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