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[/] [amber/] [trunk/] [hw/] [tests/] [swi.S] - Rev 2
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/*****************************************************************// //// Amber 2 Core Interrupt Test //// //// This file is part of the Amber project //// http://www.opencores.org/project,amber //// //// Description //// Tests the software interrupt - swi. //// //// Author(s): //// - Conor Santifort, csantifort.amber@gmail.com //// ////////////////////////////////////////////////////////////////////// //// Copyright (C) 2010 Authors and OPENCORES.ORG //// //// This source file may be used and distributed without //// restriction provided that this copyright statement is not //// removed from the file and that any derivative work contains //// the original copyright notice and the associated disclaimer. //// //// This source file is free software; you can redistribute it //// and/or modify it under the terms of the GNU Lesser General //// Public License as published by the Free Software Foundation; //// either version 2.1 of the License, or (at your option) any //// later version. //// //// This source is distributed in the hope that it will be //// useful, but WITHOUT ANY WARRANTY; without even the implied //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// PURPOSE. See the GNU Lesser General Public License for more //// details. //// //// You should have received a copy of the GNU Lesser General //// Public License along with this source; if not, download it //// from http://www.opencores.org/lgpl.shtml //// //*****************************************************************/#include "amber_registers.h".section .text.globl mainmain:/* 0x00 Reset Interrupt vector address */b start/* 0x04 Undefined Instruction Interrupt vector address */b testfail/* 0x08 SWI Interrupt vector address */b service_swi/* 0x0c Prefetch abort Interrupt vector address */b testfail/* 0x10 Data abort Interrupt vector address */b testfailb testfail/* 0x18 IRQ vector address */b testfail/* 0x1c FIRQ vector address */b testfailstart:/* Switch to User Mode *//* and unset interrupt mask bits */mov r0, #0x00000000teqp pc, r0@ Check that we're in user mode nowmov r2, pcands r2, r2, #3movne r10, #10bne testfail@ ---------------------------------@ Test a SWI that does execute@ ---------------------------------swieq #0xff8877pos1: b testpassb testfailb testfailcontinue:mov r1, #3mov r2, #2cmp r1, r2moveq r3, #17@ ---------------------------------@ Test a SWI that does not execute@ ---------------------------------swieq #0xff1122moveq r10, #20beq testfailbne testpass@ ---------------------------------@ Test Conditional Execution of SWI@ ---------------------------------service_swi:@ Check that the address immediately@ after the SWI instruction is saved@ in the supervisor mode lrldr r0, Adrpos1ldr r13, PCMaskand r14, r14, r13cmp r0, r14movne r10, #20bne testfail@ Check that we're back in supervisor mode nowmov r2, pc@ filter out all bits other than mode bitsand r2, r2, #0x3cmp r2, #0x00000003movne r10, #30bne testfail@ ------------------------------------------@ Retun after interrupt@ ------------------------------------------b continuetestfail:ldr r11, AdrTestStatusstr r10, [r11]b testfailtestpass:ldr r11, AdrTestStatusmov r10, #17str r10, [r11]b testpass@ put this data section here so its reachable@ by the 8-bit immediate offset in LDRHData1: .word 0x12345678Data2: .word 0xffccbbaaData3: .word 0xffccbbaaData4: .word 0x12345600Data5: .word 0x0000ffffData6: .word 0xffff0000Data7: .word 0x5678ffffData8: .word 0xffffffffPCMask: .word 0x03fffffc/* Write 17 to this address to generate a Test Passed message */AdrTestStatus: .word ADR_AMBER_TEST_STATUSAdrData1: .word Data1AdrData2: .word Data2AdrData3: .word Data3AdrData4: .word Data4AdrData5: .word Data5AdrData6: .word Data6AdrData7: .word Data7AdrData8: .word Data8Adrpos1: .word pos1/* ========================================================================= *//* ========================================================================= */