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https://opencores.org/ocsvn/amber/amber/trunk
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[/] [amber/] [trunk/] [hw/] [vlog/] [xs6_ddr3/] [datasheet.txt] - Rev 79
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CORE Generator Options:
Target Device : xc6slx45t-fgg484
Speed Grade : -3
HDL : verilog
Synthesis Tool : XST
MIG Output Options:
Component Name : ddr3
No of Controllers : 1
Hardware Test Bench : disabled
/*******************************************************/
/* Controller 3 */
/*******************************************************/
Controller Options :
Memory : DDR3_SDRAM
Design Clock Frequency : 2500 ps (400.00 MHz)
Memory Type : Components
Memory Part : MT41J64M16XX-187E
Equivalent Part(s) : MT41J64M16LA-187E
Row Address : 13
Column Address : 10
Bank Address : 3
Data Mask : enabled
Memory Options :
Burst Length : 8(00)
CAS Latency : 6
TDQS enable : Disabled
DLL Enable : Enable
Write Leveling Enable : Disabled
Output Drive Strength : RZQ/6
Additive Latency (AL) : 0
RTT (nominal) - ODT : RZQ/4
Auto Self Refresh : Enabled
CAS write latency : 5
Partial-Array Self Refresh : Full Array
RTT_WR : Dynamic ODT off
High Temparature Self Refresh Rate : Normal
User Interface Parameters :
Configuration Type : One 128-bit bi-directional port
Ports Selected : Port0
Memory Address Mapping : ROW_BANK_COLUMN
Arbitration Algorithm : Round Robin
Arbitration :
Time Slot0 : 0
Time Slot1 : 0
Time Slot2 : 0
Time Slot3 : 0
Time Slot4 : 0
Time Slot5 : 0
Time Slot6 : 0
Time Slot7 : 0
Time Slot8 : 0
Time Slot9 : 0
Time Slot10: 0
Time Slot11: 0
FPGA Options :
Class for Address and Control : II
Class for Data : II
Memory Interface Pin Termination : UNCALIB_TERM
DQ/DQS : 50 Ohms
Calibration Row Address : 0000
Calibration Column Address : 000
Calibration Bank Address : 0
Bypass Calibration : enabled
Debug Signals for Memory Controller : Enable
Input Clock Type : Differential
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