URL
https://opencores.org/ocsvn/amber/amber/trunk
Subversion Repositories amber
[/] [amber/] [trunk/] [hw/] [vlog/] [xs6_ddr3/] [ddr3.xco] - Rev 75
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##############################################################
#
# Xilinx Core Generator version 14.5
# Date: Sun Apr 28 12:02:09 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:mig:3.92
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc6slx45t
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Structural
SET speedgrade = -3
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT MIG_Virtex-6_and_Spartan-6 family Xilinx,_Inc. 3.92
# END Select
# BEGIN Parameters
CSET component_name=ddr3
CSET xml_input_file=./ddr3/user_design/mig.prj
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2013-03-27T03:45:13Z
# END Extra information
GENERATE
# CRC: 75718c29
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