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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc
[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [perl_gui/] [lib/] [ip/] [Other/] [fout_sim.IP] - Rev 54
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#######################################################################
## File: fout_sim.IP
##
## Copyright (C) 2014-2019 Alireza Monemi
##
## This file is part of ProNoC 1.9.1
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAVIOR.
################################################################################
$ipgen = bless( {
'version' => 29,
'sw_files' => [
'/mpsoc/src_processor/src_lib/simple-printf'
],
'modules' => {
'fout_simulator' => {}
},
'ip_name' => 'fout_sim',
'module_name' => 'fout_simulator',
'parameters' => {
'BUFFER_SIZE' => {
'content' => '10,1024,1',
'global_param' => 'Parameter',
'redefine_param' => 1,
'info' => 'Buffer width for getting for getting fle name.',
'type' => 'Spin-button',
'default' => '255 '
}
},
'hdl_files_ticked' => [],
'ports' => {
's_we_i' => {
'type' => 'input',
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'we_i',
'range' => ''
},
's_cyc_i' => {
'intfc_port' => 'cyc_i',
'type' => 'input',
'intfc_name' => 'plug:wb_slave[0]',
'range' => ''
},
's_ack_o' => {
'intfc_port' => 'ack_o',
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'output',
'range' => ''
},
's_addr_i' => {
'range' => '2 : 0',
'intfc_port' => 'adr_i',
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'input'
},
's_dat_o' => {
'range' => '31 : 0',
'intfc_port' => 'dat_o',
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'output'
},
'clk' => {
'intfc_name' => 'plug:clk[0]',
'type' => 'input',
'intfc_port' => 'clk_i',
'range' => ''
},
's_dat_i' => {
'range' => '31 : 0',
'intfc_port' => 'dat_i',
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'input'
},
's_cti_i' => {
'intfc_port' => 'cti_i',
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'input',
'range' => '2 : 0'
},
'reset' => {
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'type' => 'input',
'range' => ''
},
's_sel_i' => {
'intfc_port' => 'sel_i',
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'input',
'range' => '3 : 0'
},
's_stb_i' => {
'range' => '',
'intfc_port' => 'stb_i',
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'input'
}
},
'gui_status' => {
'status' => 'ideal',
'timeout' => 0
},
'system_c' => '#define MODE_NOT_SOPPRTED 0
#define MODE_CLOSE 1
#define MODE_W 2
#define MODE_WB 3
#define MODE_A 4
#define MODE_AB 5
FILE file_ptr [50]={0};
FILE * fopen (const char *filename, const char *mode){
//alloacte a new pointer;
int i=0;
while(file_ptr [i]!=0 && i<50) i++;
if(i==50) return ((FILE *)0) ;
//set file ,ode
if (mode[0] == \'w\' ){
if(mode[1]==\'b\') ${IP}_FILE_MODE = MODE_WB;
else ${IP}_FILE_MODE = MODE_W;
}else if (mode[0] == \'a\' ){
if(mode[1]==\'b\') ${IP}_FILE_MODE = MODE_AB;
else ${IP}_FILE_MODE = MODE_A;
}else { // not supported mode
//${IP}_FILE_MODE = MODE_NOT_SOPPRTED;
return ((FILE *)0);
}
file_ptr [i]=i+1;
//send file pointer
${IP}_GET_FLE_PTR = file_ptr [i];
//send file name
do{
${IP}_GET_FILE_NAME = *filename;
filename++;
}while(*filename!=0);
// activate the Verilog Fwrite command once sending zero
${IP}_GET_FILE_NAME = 0;
return (& file_ptr[i]);
}
void fclose(FILE * f){
//write file pointer
${IP}_GET_FLE_PTR = *f;
${IP}_FILE_MODE = MODE_CLOSE; // activate the Verilog fclose
*f = 0; //set free the pointer
}
void foutbyte( char c){
//write content
${IP}_GET_FILE_CONTENT = c;
}
void fout_select (FILE *f){
//write file pointer
${IP}_GET_FLE_PTR = *f;
}
#include "simple-printf/sim_fprintf.c"
',
'category' => 'Other',
'description' => 'A simple module to replicate the fprintf/fopen instructions in simulator enviremets. ',
'file_name' => '/home/alireza/work/git/hca_git/ProNoC/mpsoc/rtl/src_peripheral/Other/fout_simulator.v',
'unused' => {
'plug:wb_slave[0]' => [
'tag_i',
'rty_o',
'bte_i',
'err_o'
]
},
'ports_order' => [
'reset',
'clk',
's_dat_i',
's_sel_i',
's_addr_i',
's_cti_i',
's_stb_i',
's_cyc_i',
's_we_i',
's_dat_o',
's_ack_o'
],
'plugs' => {
'reset' => {
'type' => 'num',
'value' => 1,
'0' => {
'name' => 'reset'
}
},
'wb_slave' => {
'0' => {
'name' => 'wb_slave',
'width' => 5,
'addr' => '0x9000_0000 0x90ff_ffff UART16550 Controller'
},
'type' => 'num',
'value' => 1
},
'clk' => {
'value' => 1,
'type' => 'num',
'0' => {
'name' => 'clk'
}
}
},
'parameters_order' => [
'BUFFER_SIZE'
],
'hdl_files' => [
'/mpsoc/rtl/src_peripheral/Other/fout_simulator.v'
],
'system_h' => '#include "simple-printf/sim_fprintf.h"
#define ${IP}_GET_FLE_PTR (*((volatile unsigned int *) ($BASE)))
#define ${IP}_GET_FILE_NAME (*((volatile unsigned int *) ($BASE+4)))
#define ${IP}_GET_FILE_CONTENT (*((volatile unsigned int *) ($BASE+8)))
#define ${IP}_FILE_MODE (*((volatile unsigned int *) ($BASE+12)))
#define FILE char
FILE * fopen (const char *filename, const char *mode);
void fclose(FILE * f);
void foutbyte(char c);
void fout_select(FILE * f);'
}, 'ip_gen' );
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