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#######################################################################
## File: gpo.IP
##
## Copyright (C) 2014-2016 Alireza Monemi
##
## This file is part of ProNoC 1.8.0
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAIVOR.
################################################################################
$ipgen =bless( {
'sockets' => {
'jtag_to_wb' => {
'1' => {
'name' => 'jtag_to_wb_1'
},
'value' => 3,
'0' => {
'name' => 'jtag_to_wb_0'
},
'2' => {
'name' => 'jtag_to_wb_2'
},
'type' => 'num'
}
},
'hdl_files' => [],
'category' => 'Other',
'parameters' => {
'T2_ram_Aw' => {
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'info' => undef,
'type' => 'Fixed',
'default' => '14'
},
'T1_ram_Aw' => {
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => undef,
'default' => '14',
'type' => 'Fixed'
},
'T3_ram_JINDEXw' => {
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'info' => undef,
'default' => '8',
'type' => 'Fixed'
},
'T2_cpu_FEATURE_INSTRUCTIONCACHE' => {
'default' => '"ENABLED"',
'type' => 'Fixed',
'info' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => undef
},
'T0_timer_PRESCALER_WIDTH' => {
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '8',
'type' => 'Fixed',
'info' => undef
},
'T2_cpu_FEATURE_DMMU' => {
'type' => 'Fixed',
'default' => '"ENABLED"',
'info' => undef,
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'T0_ram_JINDEXw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => undef,
'default' => '8',
'type' => 'Fixed',
'info' => undef
},
'T2_led_PORT_WIDTH' => {
'default' => ' 1',
'type' => 'Fixed',
'info' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => undef
},
'T3_timer_PRESCALER_WIDTH' => {
'type' => 'Fixed',
'default' => '8',
'info' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T2_cpu_IRQ_NUM' => {
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => undef,
'type' => 'Fixed',
'default' => '32'
},
'T1_cpu_FEATURE_IMMU' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef,
'type' => 'Fixed',
'default' => '"ENABLED"',
'info' => undef
},
'T0_ram_FPGA_VENDOR' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef,
'type' => 'Fixed',
'default' => '"XILINX"',
'info' => undef
},
'T0_ram_JSTATUSw' => {
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => undef,
'default' => '8',
'type' => 'Fixed'
},
'T0_cpu_FEATURE_DMMU' => {
'info' => undef,
'type' => 'Fixed',
'default' => '"ENABLED"',
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'T1_cpu_FEATURE_DATACACHE' => {
'info' => undef,
'type' => 'Fixed',
'default' => '"ENABLED"',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T2_ram_J2WBw' => {
'default' => '(T2_ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+T2_ram_JDw+T2_ram_JAw : 1',
'type' => 'Fixed',
'info' => undef,
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'T0_cpu_OPTION_OPERAND_WIDTH' => {
'info' => undef,
'default' => '32',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => undef
},
'T2_ram_JTAG_CONNECT' => {
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => undef,
'default' => '"XILINX_JTAG_WB"',
'type' => 'Fixed'
},
'T1_cpu_OPTION_DCACHE_SNOOP' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => undef,
'type' => 'Fixed',
'default' => '"ENABLED"',
'info' => undef
},
'T0_cpu_FEATURE_DATACACHE' => {
'info' => undef,
'default' => '"ENABLED"',
'type' => 'Fixed',
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1
},
'T3_ram_JTAG_CONNECT' => {
'info' => undef,
'type' => 'Fixed',
'default' => '"XILINX_JTAG_WB"',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T3_ram_J2WBw' => {
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '(T3_ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+T3_ram_JDw+T3_ram_JAw : 1',
'type' => 'Fixed',
'info' => undef
},
'T3_ram_JDw' => {
'default' => 'T3_ram_Dw',
'type' => 'Fixed',
'info' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => undef
},
'T0_ram_JTAG_CONNECT' => {
'info' => undef,
'type' => 'Fixed',
'default' => '"XILINX_JTAG_WB"',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T0_ram_J2WBw' => {
'info' => undef,
'default' => '(T0_ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+T0_ram_JDw+T0_ram_JAw : 1',
'type' => 'Fixed',
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1
},
'T2_cpu_FEATURE_IMMU' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef,
'info' => undef,
'type' => 'Fixed',
'default' => '"ENABLED"'
},
'T1_ram_JDw' => {
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'info' => undef,
'default' => 'T1_ram_Dw',
'type' => 'Fixed'
},
'T3_cpu_OPTION_DCACHE_SNOOP' => {
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => undef,
'type' => 'Fixed',
'default' => '"ENABLED"'
},
'T1_cpu_FEATURE_INSTRUCTIONCACHE' => {
'type' => 'Fixed',
'default' => '"ENABLED"',
'info' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T1_ram_JAw' => {
'type' => 'Fixed',
'default' => '32',
'info' => undef,
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1
},
'T3_led_PORT_WIDTH' => {
'default' => ' 1',
'type' => 'Fixed',
'info' => undef,
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1
},
'T1_ram_Dw' => {
'default' => '32',
'type' => 'Fixed',
'info' => undef,
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'T0_ram_WB2Jw' => {
'info' => undef,
'type' => 'Fixed',
'default' => '(T0_ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+T0_ram_JSTATUSw+T0_ram_JINDEXw+1+T0_ram_JDw : 1',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T2_cpu_OPTION_DCACHE_SNOOP' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => undef,
'info' => undef,
'default' => '"ENABLED"',
'type' => 'Fixed'
},
'T1_ram_WB2Jw' => {
'info' => undef,
'default' => '(T1_ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+T1_ram_JSTATUSw+T1_ram_JINDEXw+1+T1_ram_JDw : 1',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T0_ram_Aw' => {
'type' => 'Fixed',
'default' => '14',
'info' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T1_cpu_IRQ_NUM' => {
'default' => '32',
'type' => 'Fixed',
'info' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => undef
},
'T1_ram_FPGA_VENDOR' => {
'type' => 'Fixed',
'default' => '"XILINX"',
'info' => undef,
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1
},
'T3_ram_WB2Jw' => {
'default' => '(T3_ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+T3_ram_JSTATUSw+T3_ram_JINDEXw+1+T3_ram_JDw : 1',
'type' => 'Fixed',
'info' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T2_ram_JINDEXw' => {
'default' => '8',
'type' => 'Fixed',
'info' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T3_cpu_FEATURE_DATACACHE' => {
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '"ENABLED"',
'info' => undef
},
'T0_cpu_FEATURE_INSTRUCTIONCACHE' => {
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => undef,
'type' => 'Fixed',
'default' => '"ENABLED"'
},
'T2_cpu_FEATURE_DATACACHE' => {
'default' => '"ENABLED"',
'type' => 'Fixed',
'info' => undef,
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'T2_ram_FPGA_VENDOR' => {
'type' => 'Fixed',
'default' => '"XILINX"',
'info' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T2_ram_JSTATUSw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => undef,
'type' => 'Fixed',
'default' => '8',
'info' => undef
},
'T3_ram_Aw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef,
'info' => undef,
'type' => 'Fixed',
'default' => '14'
},
'T1_ram_J2WBw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => undef,
'type' => 'Fixed',
'default' => '(T1_ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+T1_ram_JDw+T1_ram_JAw : 1',
'info' => undef
},
'T1_cpu_FEATURE_DMMU' => {
'info' => undef,
'type' => 'Fixed',
'default' => '"ENABLED"',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => undef
},
'T3_ram_FPGA_VENDOR' => {
'type' => 'Fixed',
'default' => '"XILINX"',
'info' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => undef
},
'T2_cpu_OPTION_OPERAND_WIDTH' => {
'info' => undef,
'type' => 'Fixed',
'default' => '32',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T3_cpu_FEATURE_DMMU' => {
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '"ENABLED"',
'type' => 'Fixed',
'info' => undef
},
'T0_ram_Dw' => {
'info' => undef,
'default' => '32',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T0_ram_JAw' => {
'default' => '32',
'type' => 'Fixed',
'info' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T0_cpu_IRQ_NUM' => {
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed',
'default' => '32',
'info' => undef
},
'T3_cpu_FEATURE_INSTRUCTIONCACHE' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef,
'info' => undef,
'type' => 'Fixed',
'default' => '"ENABLED"'
},
'T1_ram_JTAG_CONNECT' => {
'type' => 'Fixed',
'default' => '"XILINX_JTAG_WB"',
'info' => undef,
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1
},
'T3_ram_JSTATUSw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => undef,
'default' => '8',
'type' => 'Fixed',
'info' => undef
},
'T0_cpu_FEATURE_IMMU' => {
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed',
'default' => '"ENABLED"',
'info' => undef
},
'T0_ram_JDw' => {
'info' => undef,
'default' => 'T0_ram_Dw',
'type' => 'Fixed',
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'T3_cpu_IRQ_NUM' => {
'default' => '32',
'type' => 'Fixed',
'info' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T1_timer_PRESCALER_WIDTH' => {
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '8',
'info' => undef
},
'T2_ram_WB2Jw' => {
'default' => '(T2_ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+T2_ram_JSTATUSw+T2_ram_JINDEXw+1+T2_ram_JDw : 1',
'type' => 'Fixed',
'info' => undef,
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'T1_ram_JINDEXw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef,
'default' => '8',
'type' => 'Fixed',
'info' => undef
},
'T2_ram_Dw' => {
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'default' => '32',
'type' => 'Fixed',
'info' => undef
},
'T3_cpu_OPTION_OPERAND_WIDTH' => {
'default' => '32',
'type' => 'Fixed',
'info' => undef,
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'T2_ram_JDw' => {
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => 'T2_ram_Dw',
'info' => undef
},
'T2_ram_JAw' => {
'info' => undef,
'type' => 'Fixed',
'default' => '32',
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'T0_cpu_OPTION_DCACHE_SNOOP' => {
'info' => undef,
'type' => 'Fixed',
'default' => '"ENABLED"',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => undef
},
'T2_timer_PRESCALER_WIDTH' => {
'info' => undef,
'type' => 'Fixed',
'default' => '8',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T3_ram_JAw' => {
'info' => undef,
'type' => 'Fixed',
'default' => '32',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T1_led_PORT_WIDTH' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef,
'type' => 'Fixed',
'default' => ' 1',
'info' => undef
},
'T1_ram_JSTATUSw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef,
'info' => undef,
'type' => 'Fixed',
'default' => '8'
},
'T3_ram_Dw' => {
'info' => undef,
'default' => '32',
'type' => 'Fixed',
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'T3_cpu_FEATURE_IMMU' => {
'type' => 'Fixed',
'default' => '"ENABLED"',
'info' => undef,
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1
},
'T0_led_PORT_WIDTH' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef,
'type' => 'Fixed',
'default' => ' 1',
'info' => undef
},
'T1_cpu_OPTION_OPERAND_WIDTH' => {
'type' => 'Fixed',
'default' => '32',
'info' => undef,
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1
}
},
'parameters_order' => [
'cpu_FEATURE_DATACACHE',
'cpu_FEATURE_DMMU',
'cpu_FEATURE_IMMU',
'cpu_FEATURE_INSTRUCTIONCACHE',
'cpu_IRQ_NUM',
'cpu_OPTION_DCACHE_SNOOP',
'cpu_OPTION_OPERAND_WIDTH',
'led_PORT_WIDTH',
'ram_Aw',
'ram_Dw',
'ram_FPGA_VENDOR',
'ram_J2WBw',
'ram_JAw',
'ram_JDw',
'ram_JINDEXw',
'ram_JSTATUSw',
'ram_JTAG_CONNECT',
'ram_WB2Jw',
'timer_PRESCALER_WIDTH'
],
'file_name' => undef,
'ports' => {
'T0_ram_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'type' => 'input',
'intfc_port' => 'jwb_i',
'range' => 'T0_ram_J2WBw-1 : 0'
},
'T1_ram_jtag_to_wb' => {
'range' => 'T1_ram_J2WBw-1 : 0',
'intfc_port' => 'jwb_i',
'type' => 'input',
'intfc_name' => 'socket:jtag_to_wb[1]'
},
'T2_ram_jtag_to_wb' => {
'type' => 'input',
'intfc_name' => 'socket:jtag_to_wb[2]',
'range' => 'T2_ram_J2WBw-1 : 0',
'intfc_port' => 'jwb_i'
},
'T3_ram_wb_to_jtag' => {
'type' => 'output',
'intfc_name' => 'socket:jtag_to_wb[3]',
'range' => 'T3_ram_WB2Jw-1 : 0',
'intfc_port' => 'jwb_o'
},
'T1_ram_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'range' => 'T1_ram_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[1]',
'type' => 'output'
},
'clk1' => {
'range' => undef,
'intfc_port' => 'clk_i',
'type' => 'input',
'intfc_name' => 'plug:clk[1]'
},
'T3_led_port_o' => {
'intfc_name' => 'IO',
'type' => 'output',
'intfc_port' => 'IO',
'range' => 'T3_led_PORT_WIDTH-1 : 0'
},
'hh' => {
'type' => 'input',
'intfc_name' => 'plug:clk[0]',
'range' => undef,
'intfc_port' => 'clk_i'
},
'reset0' => {
'range' => undef,
'intfc_port' => 'reset_i',
'type' => 'input',
'intfc_name' => 'plug:reset[0]'
},
'T0_ram_wb_to_jtag' => {
'type' => 'output',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T0_ram_WB2Jw-1 : 0',
'intfc_port' => 'jwb_o'
},
'T1_led_port_o' => {
'intfc_name' => 'IO',
'type' => 'output',
'intfc_port' => 'IO',
'range' => 'T1_led_PORT_WIDTH-1 : 0'
},
'T2_ram_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'range' => 'T2_ram_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[2]',
'type' => 'output'
},
'T0_led_port_o' => {
'type' => 'output',
'intfc_name' => 'IO',
'range' => 'T0_led_PORT_WIDTH-1 : 0',
'intfc_port' => 'IO'
},
'T3_ram_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[3]',
'type' => 'input',
'intfc_port' => 'jwb_i',
'range' => 'T3_ram_J2WBw-1 : 0'
},
'enable0' => {
'intfc_port' => 'enable_i',
'range' => undef,
'intfc_name' => 'plug:enable[0]',
'type' => 'input'
},
'T2_led_port_o' => {
'type' => 'output',
'intfc_name' => 'IO',
'range' => 'T2_led_PORT_WIDTH-1 : 0',
'intfc_port' => 'IO'
}
},
'plugs' => {
'clk' => {
'0' => {
'name' => 'hh'
},
'value' => '2',
'1' => {
'name' => 'clk1'
},
'type' => 'num'
},
'reset' => {
'type' => 'num',
'0' => {
'name' => 'reset0'
},
'value' => 1
},
'enable' => {
'type' => 'num',
'0' => {
'name' => 'enable0'
},
'value' => 1
}
},
'ports_order' => [],
'ip_name' => 'noc_based_mpsoc',
'module_name' => 'noc_based_mpsoc'
}, 'ip_gen' );