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<defines>
`define CMD_INC_DEC         #AUTOGEN_NEXT_CMD

`define CMDEX_INC_DEC_implicit              4'd0
`define CMDEX_INC_DEC_increment_implicit    4'd0
`define CMDEX_INC_DEC_decrement_implicit    4'd1
`define CMDEX_INC_DEC_modregrm              4'd2
`define CMDEX_INC_DEC_increment_modregrm    4'd2
`define CMDEX_INC_DEC_decrement_modregrm    4'd3
</defines>

<decode>
dec_ready_one && decoder[7:4] == 4'h4
`CMD_INC_DEC
SET(dec_cmdex, `CMDEX_INC_DEC_increment_implicit | { 3'd0, decoder[3] });
SET(consume_one);
</decode>

<decode>
dec_ready_modregrm_one && { decoder[7:1], 1'b0 } == 8'hFE && { decoder[13:12], 1'b0 } == 3'b000
prefix_group_1_lock && `DEC_MODREGRM_IS_MOD_11
`CMD_INC_DEC
SET(dec_cmdex, `CMDEX_INC_DEC_increment_modregrm | { 3'd0, decoder[11] });
IF(decoder[0] == 1'b0); SET(dec_is_8bit); ENDIF();
SET(consume_modregrm_one);
</decode>

<read>
IF(rd_cmd == `CMD_INC_DEC && { rd_cmdex[3:1], 1'b0 } == `CMDEX_INC_DEC_modregrm);
    
    SET(rd_req_eflags);

    SET(rd_src_is_1);
    
    // dst: reg, src: reg
    IF(rd_modregrm_mod == 2'b11);

        IF(rd_mutex_busy_modregrm_rm); SET(rd_waiting);
        ELSE();
            // reg, reg
            
            SET(rd_dst_is_rm);
            
            SET(rd_req_rm);
        ENDIF();
    ENDIF();

    // dst: memory, src: reg
    IF(rd_modregrm_mod != 2'b11);

        SET(rd_dst_is_memory);
        
        SET(rd_req_memory);
    
        IF(rd_mutex_busy_memory); SET(rd_waiting);
        ELSE();
            SET(read_rmw_virtual);
            
            IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();
        ENDIF();
    ENDIF();
ENDIF();
</read>

<read>
IF(rd_cmd == `CMD_INC_DEC && { rd_cmdex[3:1], 1'b0 } == `CMDEX_INC_DEC_implicit);
    
    SET(rd_src_is_1);
    SET(rd_dst_is_implicit_reg);

    SET(rd_req_eflags);
    SET(rd_req_implicit_reg);
    
    // dst: implicit reg, src: imm
    IF(rd_mutex_busy_implicit_reg); SET(rd_waiting); ENDIF();
ENDIF();
</read>

<execute>
IF(exe_cmd == `CMD_INC_DEC);
    
    SET(exe_arith_index, (exe_cmdex[0] == `FALSE)? (`ARITH_VALID | `ARITH_ADD) : (`ARITH_VALID | `ARITH_SUB));

    SET(exe_result, (exe_cmdex[0] == `FALSE)? exe_arith_add[31:0] : exe_arith_sub[31:0]);

ENDIF();
</execute>

<write>
IF(wr_cmd == `CMD_INC_DEC);
    
    IF(wr_dst_is_memory && ~(write_for_wr_ready)); SET(wr_waiting); ENDIF();

    SET(write_rmw_virtual,   wr_dst_is_memory);
    SET(write_regrm,         wr_dst_is_implicit_reg || wr_dst_is_rm);  

    // no carry flag
    SAVE(zflag, zflag_result);
    SAVE(sflag, sflag_result);
    SAVE(pflag, pflag_result);

    SAVE(aflag, aflag_arith);
    SAVE(oflag, oflag_arith);
ENDIF();  
</write>