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https://opencores.org/ocsvn/ao486/ao486/trunk
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[/] [ao486/] [trunk/] [rtl/] [ao486/] [commands/] [CMD_MOV.txt] - Rev 2
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<defines>
`define CMD_MOV #AUTOGEN_NEXT_CMD
`define CMDEX_MOV_immediate 4'd0
`define CMDEX_MOV_modregrm 4'd1
`define CMDEX_MOV_modregrm_imm 4'd2
`define CMDEX_MOV_memoffset 4'd3
</defines>
<decode>
dec_ready_mem_offset && { decoder[7:2], 2'b0 } == 8'hA0
`CMD_MOV
SET(dec_cmdex, `CMDEX_MOV_memoffset);
IF(decoder[0] == 1'b0); SET(dec_is_8bit); ENDIF();
SET(consume_mem_offset);
</decode>
<decode>
dec_ready_one_imm && decoder[7:4] == 4'hB
`CMD_MOV
SET(dec_cmdex, `CMDEX_MOV_immediate);
IF(decoder[3] == 1'b0); SET(dec_is_8bit); ENDIF();
SET(consume_one_imm);
</decode>
<decode>
dec_ready_modregrm_one && { decoder[7:2], 2'b0 } == 8'h88
`CMD_MOV
SET(dec_cmdex, `CMDEX_MOV_modregrm);
IF(decoder[0] == 1'b0); SET(dec_is_8bit); ENDIF();
SET(consume_modregrm_one);
</decode>
<decode>
dec_ready_modregrm_imm && { decoder[7:1], 1'b0 } == 8'hC6 && decoder[13:11] == 3'd0
`CMD_MOV
SET(dec_cmdex, `CMDEX_MOV_modregrm_imm);
IF(decoder[0] == 1'b0); SET(dec_is_8bit); ENDIF();
SET(consume_modregrm_imm);
</decode>
<read>
IF(rd_cmd == `CMD_MOV && rd_cmdex == `CMDEX_MOV_memoffset);
SET(address_memoffset);
// dst: eAX, src: mem
IF(~(rd_decoder[1]));
SET(rd_src_is_memory);
SET(rd_dst_is_eax);
SET(rd_req_eax);
IF(rd_mutex_busy_memory); SET(rd_waiting);
ELSE();
SET(read_virtual);
IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();
ENDIF();
// dst: mem, src: eAX
ELSE();
SET(rd_src_is_eax);
SET(rd_dst_is_memory);
SET(rd_req_memory);
SET(write_virtual_check);
IF(rd_mutex_busy_eax || ~(write_virtual_check_ready)); SET(rd_waiting); ENDIF();
ENDIF();
ENDIF();
</read>
<read>
IF(rd_cmd == `CMD_MOV && rd_cmdex == `CMDEX_MOV_modregrm && rd_decoder[1]);
SET(rd_dst_is_reg);
SET(rd_req_reg);
// dst: reg, src: reg
IF(rd_modregrm_mod == 2'b11);
SET(rd_src_is_rm);
IF(rd_mutex_busy_modregrm_rm); SET(rd_waiting); ENDIF();
ENDIF();
// dst: reg, src: memory
IF(rd_modregrm_mod != 2'b11);
SET(rd_src_is_memory);
IF(rd_mutex_busy_memory); SET(rd_waiting);
ELSE();
SET(read_virtual);
IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();
ENDIF();
ENDIF();
ENDIF();
</read>
<read>
IF(rd_cmd == `CMD_MOV && rd_cmdex == `CMDEX_MOV_modregrm && ~(rd_decoder[1]));
SET(rd_src_is_reg);
// dst: reg, src: reg
IF(rd_modregrm_mod == 2'b11);
SET(rd_dst_is_rm);
SET(rd_req_rm);
IF(rd_mutex_busy_modregrm_reg); SET(rd_waiting); ENDIF();
ENDIF();
// dst: memory, src: reg
IF(rd_modregrm_mod != 2'b11);
SET(rd_dst_is_memory);
SET(rd_req_memory);
IF(rd_mutex_busy_modregrm_reg); SET(rd_waiting);
ELSE();
SET(write_virtual_check);
IF(~(write_virtual_check_ready)); SET(rd_waiting); ENDIF();
ENDIF();
ENDIF();
ENDIF();
</read>
<read>
IF(rd_cmd == `CMD_MOV && rd_cmdex == `CMDEX_MOV_modregrm_imm);
SET(rd_src_is_modregrm_imm);
// dst: reg, src: imm
IF(rd_modregrm_mod == 2'b11);
SET(rd_dst_is_rm);
SET(rd_req_rm);
IF(rd_mutex_busy_modregrm_reg); SET(rd_waiting); ENDIF();
ENDIF();
// dst: memory, src: imm
IF(rd_modregrm_mod != 2'b11);
SET(rd_dst_is_memory);
SET(rd_req_memory);
IF(rd_mutex_busy_modregrm_reg); SET(rd_waiting);
ELSE();
SET(write_virtual_check);
IF(~(write_virtual_check_ready)); SET(rd_waiting); ENDIF();
ENDIF();
ENDIF();
ENDIF();
</read>
<read>
IF(rd_cmd == `CMD_MOV && rd_cmdex == `CMDEX_MOV_immediate);
SET(rd_src_is_imm);
SET(rd_dst_is_implicit_reg);
SET(rd_req_implicit_reg);
ENDIF();
</read>
<execute>
IF(exe_cmd == `CMD_MOV); // `CMDEX_MEMOFFSET || `CMDEX_MODREGRM || `CMDEX_MODREGRM_IMM || `CMDEX_IMPLICIT
SET(exe_result, src);
SET(exe_result2, dst);
ENDIF();
</execute>
<write>
IF(wr_cmd == `CMD_MOV);
IF(wr_dst_is_memory && ~(write_for_wr_ready)); SET(wr_waiting); ENDIF();
SET(write_eax, wr_dst_is_eax);
SET(write_virtual, wr_dst_is_memory);
SET(write_regrm, wr_dst_is_reg || wr_dst_is_rm || wr_dst_is_implicit_reg);
ENDIF();
</write>