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<defines>
`define CMD_MOV_to_seg      #AUTOGEN_NEXT_CMD

`define CMD_LLDT            #AUTOGEN_NEXT_CMD

`define CMD_LTR             #AUTOGEN_NEXT_CMD

`define CMDEX_MOV_to_seg_LLDT_LTR_STEP_1     4'd0
`define CMDEX_MOV_to_seg_LLDT_LTR_STEP_LAST  4'd1
</defines>

<decode>
dec_ready_modregrm_one && decoder[7:0] == 8'h8E
prefix_group_1_lock || decoder[13:11] >= 3'd6 || decoder[13:11] == 3'd1
`CMD_MOV_to_seg
SET(dec_cmdex, `CMDEX_MOV_to_seg_LLDT_LTR_STEP_1);
SET(consume_modregrm_one);
SET(dec_is_complex);
</decode>

<decode>
dec_ready_2byte_modregrm && decoder[7:0] == 8'h00 && decoder[13:11] == 3'd2
prefix_group_1_lock || ~(protected_mode)
`CMD_LLDT
SET(dec_cmdex, `CMDEX_MOV_to_seg_LLDT_LTR_STEP_1);
SET(consume_modregrm_one);
SET(dec_is_complex);
</decode>

<decode>
dec_ready_2byte_modregrm && decoder[7:0] == 8'h00 && decoder[13:11] == 3'd3
prefix_group_1_lock || ~(protected_mode)
`CMD_LTR
SET(dec_cmdex, `CMDEX_MOV_to_seg_LLDT_LTR_STEP_1);
SET(consume_modregrm_one);
SET(dec_is_complex);
</decode>


<microcode>
IF((mc_cmd == `CMD_MOV_to_seg || mc_cmd == `CMD_LLDT || mc_cmd == `CMD_LTR) && mc_cmdex_last != `CMDEX_MOV_to_seg_LLDT_LTR_STEP_LAST);
    CALL(`CMDEX_load_seg_STEP_1);
    `CMDEX_MOV_to_seg_LLDT_LTR_STEP_LAST
ENDIF();

IF((mc_cmd == `CMD_MOV_to_seg || mc_cmd == `CMD_LLDT || mc_cmd == `CMD_LTR) && mc_cmdex_last == `CMDEX_MOV_to_seg_LLDT_LTR_STEP_LAST);
    `CMDEX_MOV_to_seg_LLDT_LTR_STEP_LAST
ENDIF();
</microcode>

<read>
IF((rd_cmd == `CMD_MOV_to_seg || rd_cmd == `CMD_LLDT || rd_cmd == `CMD_LTR) && rd_cmdex == `CMDEX_MOV_to_seg_LLDT_LTR_STEP_1);
            
    IF(rd_cmd == `CMD_MOV_to_seg || cpl == 2'd0);
    
        // dst: seg, src: rm
        IF(rd_modregrm_mod == 2'b11);
            
            IF(rd_mutex_busy_modregrm_rm); SET(rd_waiting); ENDIF();
        
            SET(rd_dst_is_rm);

            IF(rd_cmd == `CMD_MOV_to_seg);
                SET(rd_glob_param_1_set);
                SET(rd_glob_param_1_value, { 13'd0, rd_decoder[13:11], dst_wire[15:0] });
            ENDIF();
            
            IF(rd_cmd == `CMD_LLDT);
                SET(rd_glob_param_1_set);
                SET(rd_glob_param_1_value, { 13'd0, `SEGMENT_LDT, dst_wire[15:0] });
            ENDIF();
            
            IF(rd_cmd == `CMD_LTR);
                SET(rd_glob_param_1_set);
                SET(rd_glob_param_1_value, { 13'd0, `SEGMENT_TR, dst_wire[15:0] });
            ENDIF();
        ENDIF();

        // dst: memory, src: seg
        IF(rd_modregrm_mod != 2'b11);
            
            SET(read_length_word);
        
            IF(rd_mutex_busy_memory); SET(rd_waiting);
            ELSE();
                IF(rd_cmd == `CMD_MOV_to_seg);
                    SET(rd_glob_param_1_set);
                    SET(rd_glob_param_1_value, { 13'd0, rd_decoder[13:11], read_4[15:0] });
                ENDIF();
                
                IF(rd_cmd == `CMD_LLDT);
                    SET(rd_glob_param_1_set);
                    SET(rd_glob_param_1_value, { 13'd0, `SEGMENT_LDT, read_4[15:0] });
                ENDIF();
                
                IF(rd_cmd == `CMD_LTR);
                    SET(rd_glob_param_1_set);
                    SET(rd_glob_param_1_value, { 13'd0, `SEGMENT_TR, read_4[15:0] });
                ENDIF();

                SET(read_virtual);

                IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();
            ENDIF();
        ENDIF();
    ENDIF();
ENDIF();
</read>

<execute>
IF((exe_cmd == `CMD_LLDT || exe_cmd == `CMD_LTR) && exe_cmdex == `CMDEX_MOV_to_seg_LLDT_LTR_STEP_1);
    IF(cpl != 2'd0);
        SET(exe_waiting);
        SET(exe_trigger_gp_fault); //exception GP(0)
    ENDIF();
ENDIF();
</execute>

<write>
IF((wr_cmd == `CMD_MOV_to_seg || wr_cmd == `CMD_LLDT || wr_cmd == `CMD_LTR) && wr_cmdex == `CMDEX_MOV_to_seg_LLDT_LTR_STEP_1);
    SET(wr_not_finished);
ENDIF();
</write>

<write>
IF((wr_cmd == `CMD_MOV_to_seg || wr_cmd == `CMD_LLDT || wr_cmd == `CMD_LTR) && wr_cmdex == `CMDEX_MOV_to_seg_LLDT_LTR_STEP_LAST);
    
    IF(wr_cmd == `CMD_MOV_to_seg && wr_decoder[13:11] == `SEGMENT_SS); SET(wr_inhibit_interrupts_and_debug); ENDIF();
    
    // clear pipeline
    SET(wr_req_reset_micro);
    SET(wr_req_reset_rd);
    SET(wr_req_reset_exe);
ENDIF();
</write>