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[/] [ao486/] [trunk/] [rtl/] [ao486/] [commands/] [CMD_XADD.txt] - Rev 8
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<defines>
`define CMD_XADD #AUTOGEN_NEXT_CMD
`define CMDEX_XADD_FIRST 4'd0
`define CMDEX_XADD_LAST 4'd1
</defines>
<decode>
dec_ready_2byte_modregrm && { decoder[7:1], 1'b0 } == 8'hC0
prefix_group_1_lock && `DEC_MODREGRM_IS_MOD_11
`CMD_XADD
IF(decoder[0] == 1'b0); SET(dec_is_8bit); ENDIF();
SET(consume_modregrm_one);
SET(dec_is_complex);
</decode>
<microcode>
`CMDEX_XADD_FIRST
LAST(`CMDEX_XADD_LAST);
</microcode>
<read>
IF(rd_cmd == `CMD_XADD && rd_cmdex == `CMDEX_XADD_FIRST);
SET(rd_src_is_reg);
// dst: reg, src: reg
IF(rd_modregrm_mod == 2'b11);
SET(rd_dst_is_rm);
IF(rd_mutex_busy_modregrm_reg || rd_mutex_busy_modregrm_rm); SET(rd_waiting); ENDIF();
ENDIF();
// dst: memory, src: reg
IF(rd_modregrm_mod != 2'b11);
SET(rd_dst_is_memory);
IF(rd_mutex_busy_modregrm_reg || rd_mutex_busy_memory); SET(rd_waiting);
ELSE();
SET(read_rmw_virtual);
IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();
ENDIF();
ENDIF();
ENDIF();
</read>
<read>
IF(rd_cmd == `CMD_XADD && rd_cmdex == `CMDEX_XADD_LAST);
SET(rd_dst_is_reg);
SET(rd_req_reg);
SET(rd_req_eflags);
SET(rd_req_rm, rd_modregrm_mod == 2'b11);
SET(rd_req_memory, rd_modregrm_mod != 2'b11);
ENDIF();
</read>
<execute>
IF(exe_cmd == `CMD_XADD && exe_cmdex == `CMDEX_XADD_FIRST);
SET(exe_arith_index, (`ARITH_VALID | `ARITH_ADD));
SET(exe_result, exe_arith_add[31:0]);
SAVE(exe_buffer, dst);
ENDIF();
</execute>
<execute>
IF(exe_cmd == `CMD_XADD && exe_cmdex == `CMDEX_XADD_LAST);
SET(exe_result, exe_buffer);
ENDIF();
</execute>
<write>
IF(wr_cmd == `CMD_XADD && wr_cmdex == `CMDEX_XADD_FIRST);
IF(wr_dst_is_memory && ~(write_for_wr_ready)); SET(wr_waiting); ENDIF();
SET(write_regrm, wr_dst_is_rm);
SET(write_rmw_virtual, wr_dst_is_memory);
SAVE(zflag, zflag_result);
SAVE(sflag, sflag_result);
SAVE(pflag, pflag_result);
SAVE(aflag, aflag_arith);
SAVE(cflag, cflag_arith);
SAVE(oflag, oflag_arith);
SET(wr_not_finished);
ENDIF();
</write>
<write>
IF(wr_cmd == `CMD_XADD && wr_cmdex == `CMDEX_XADD_LAST);
IF(wr_modregrm_mod != 2'b11 || wr_modregrm_reg != wr_modregrm_rm);
SET(write_regrm);
ENDIF();
ENDIF();
</write>
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