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[/] [ao486/] [trunk/] [rtl/] [ao486/] [commands/] [CMD_task_switch.txt] - Rev 8
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<defines>
`define TASK_SWITCH_FROM_IRET 2'd0
`define TASK_SWITCH_FROM_INT 2'd1
`define TASK_SWITCH_FROM_CALL 2'd2
`define TASK_SWITCH_FROM_JUMP 2'd3
`define TASK_SWITCH_SOURCE_BITS 17:16
//------------------------------------------------------------------------------
`define CMD_task_switch #AUTOGEN_NEXT_CMD
// glob_param_1[15:0] --> new_tr
// glob_param_1[17:16] --> source
// glob_param_2 --> [used internal]
// glob_param_3[15:0] --> error_code
// glob_param_3[16] --> push code flag
// glob_param_3[17] --> [internal] is push 32 bit (TSS386)
// glob_param_3[21:18] --> cmd_len
// glob_descriptor --> new_tr_cache
`define CMDEX_task_switch_STEP_1 4'd1
// check limits
`define CMDEX_task_switch_STEP_2 4'd2
`define CMDEX_task_switch_STEP_3 4'd3
`define CMDEX_task_switch_STEP_4 4'd4
`define CMDEX_task_switch_STEP_5 4'd5
// check translation for new tss
`define CMDEX_task_switch_STEP_6 4'd6
// turn off busy descriptor type
`define CMDEX_task_switch_STEP_7 4'd7
`define CMDEX_task_switch_STEP_8 4'd8
// check translation for old tss
`define CMDEX_task_switch_STEP_9 4'd9
`define CMDEX_task_switch_STEP_10 4'd10
// write old eip,eflags
`define CMDEX_task_switch_STEP_11 4'd11
// write link
`define CMDEX_task_switch_STEP_12 4'd12
`define CMDEX_task_switch_STEP_13 4'd13
`define CMDEX_task_switch_STEP_14 4'd14
// read cr3,eip,eflags
//------------------------------------------------------------------------------
`define CMD_task_switch_2 #AUTOGEN_NEXT_CMD
`define CMDEX_task_switch_2_STEP_0 4'd0
`define CMDEX_task_switch_2_STEP_7 4'd7
`define CMDEX_task_switch_2_STEP_11 4'd11
`define CMDEX_task_switch_2_STEP_13 4'd13
//------------------------------------------------------------------------------
`define CMD_task_switch_3 #AUTOGEN_NEXT_CMD
`define CMDEX_task_switch_3_STEP_0 4'd0
`define CMDEX_task_switch_3_STEP_7 4'd7
`define CMDEX_task_switch_3_STEP_8 4'd8
`define CMDEX_task_switch_3_STEP_12 4'd12
`define CMDEX_task_switch_3_STEP_15 4'd15
//------------------------------------------------------------------------------
`define CMD_task_switch_4 #AUTOGEN_NEXT_CMD
`define CMDEX_task_switch_4_STEP_0 4'd0
`define CMDEX_task_switch_4_STEP_1 4'd1
`define CMDEX_task_switch_4_STEP_2 4'd2
`define CMDEX_task_switch_4_STEP_3 4'd3
`define CMDEX_task_switch_4_STEP_4 4'd4
`define CMDEX_task_switch_4_STEP_5 4'd5
`define CMDEX_task_switch_4_STEP_6 4'd6
`define CMDEX_task_switch_4_STEP_7 4'd7
`define CMDEX_task_switch_4_STEP_8 4'd8
`define CMDEX_task_switch_4_STEP_9 4'd9
`define CMDEX_task_switch_4_STEP_10 4'd10
</defines>
<microcode>
IF(`CMDEX_task_switch_STEP_1 && cr0_pg);
`CMDEX_task_switch_STEP_2
`CMDEX_task_switch_STEP_3
IF(`CMDEX_task_switch_STEP_3 && (glob_param_1[`TASK_SWITCH_SOURCE_BITS] == `TASK_SWITCH_FROM_CALL || glob_param_1[`TASK_SWITCH_SOURCE_BITS] == `TASK_SWITCH_FROM_INT));
`CMDEX_task_switch_STEP_4
`CMDEX_task_switch_STEP_5
`CMDEX_task_switch_STEP_6
ENDIF();
IF(`CMDEX_task_switch_STEP_3 && ~(glob_param_1[`TASK_SWITCH_SOURCE_BITS] == `TASK_SWITCH_FROM_CALL || glob_param_1[`TASK_SWITCH_SOURCE_BITS] == `TASK_SWITCH_FROM_INT));
`CMDEX_task_switch_STEP_6
ENDIF();
ENDIF();
IF(`CMDEX_task_switch_STEP_1 && ~(cr0_pg));
`CMDEX_task_switch_STEP_6
ENDIF();
IF(`CMDEX_task_switch_STEP_6 && cr0_pg);
`CMDEX_task_switch_STEP_7
`CMDEX_task_switch_STEP_8
`CMDEX_task_switch_STEP_9
ENDIF();
IF(`CMDEX_task_switch_STEP_6 && ~(cr0_pg));
`CMDEX_task_switch_STEP_9
ENDIF();
IF(`CMDEX_task_switch_STEP_9);
`CMDEX_task_switch_STEP_10
`CMDEX_task_switch_2_STEP_0
IF(mc_cmd == `CMD_task_switch_2 && mc_cmdex_last < `CMDEX_task_switch_2_STEP_13);
DIRECT(mc_cmd, mc_cmdex_last + 4'd1);
ENDIF();
IF(`CMDEX_task_switch_2_STEP_13);
`CMDEX_task_switch_STEP_11
`CMDEX_task_switch_STEP_12
`CMDEX_task_switch_STEP_13
`CMDEX_task_switch_STEP_14
`CMDEX_task_switch_3_STEP_0
ENDIF();
ENDIF();
IF(mc_cmd == `CMD_task_switch_3);
DIRECT(mc_cmd, mc_cmdex_last + 4'd1);
ENDIF();
IF(`CMDEX_task_switch_3_STEP_15);
`CMDEX_task_switch_4_STEP_0
ENDIF();
IF(mc_cmd == `CMD_task_switch_4 && mc_cmdex_last < `CMDEX_task_switch_4_STEP_10);
DIRECT(mc_cmd, mc_cmdex_last + 4'd1);
ENDIF();
IF(`CMDEX_task_switch_4_STEP_10)
LOOP(`CMDEX_task_switch_4_STEP_10);
ENDIF();
</microcode>
<read_local>
wire [31:0] rd_task_switch_linear_next;
reg [31:0] rd_task_switch_linear_reg;
assign rd_task_switch_linear_next =
(glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? rd_task_switch_linear_reg + 32'd2 :
rd_task_switch_linear_reg + 32'd4;
always @(posedge clk or negedge rst_n) begin
if(rst_n == 1'b0) rd_task_switch_linear_reg <= 32'd0;
else if(rd_cmd == `CMD_task_switch && rd_cmdex == `CMDEX_task_switch_STEP_12) rd_task_switch_linear_reg <= rd_system_linear;
else if(rd_ready) rd_task_switch_linear_reg <= rd_task_switch_linear_next;
end
</read_local>
<read>
IF(rd_cmd == `CMD_task_switch && rd_cmdex == `CMDEX_task_switch_STEP_6);
SET(rd_system_linear, gdtr_base + { 16'd0, tr[15:3], 3'd0 } + 32'd4);
IF(rd_mutex_busy_active); SET(rd_waiting); // wait for previous step -- exception possible
ELSE();
IF(glob_param_1[`TASK_SWITCH_SOURCE_BITS] == `TASK_SWITCH_FROM_JUMP || glob_param_1[`TASK_SWITCH_SOURCE_BITS] == `TASK_SWITCH_FROM_IRET);
SET(rd_req_memory);
SET(rd_glob_param_2_set);
SET(rd_glob_param_2_value, read_4);
IF(rd_mutex_busy_memory); SET(rd_waiting);
ELSE();
SET(read_rmw_system_dword);
IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();
ENDIF();
ENDIF();
ENDIF();
ENDIF();
</read>
<read>
IF(rd_cmd == `CMD_task_switch && rd_cmdex == `CMDEX_task_switch_STEP_9);
IF(rd_mutex_busy_memory); SET(rd_waiting); ENDIF();
ENDIF();
</read>
<read>
IF(rd_cmd == `CMD_task_switch_2 && rd_cmdex <= `CMDEX_task_switch_2_STEP_7);
SET(rd_src_is_cmdex);
ENDIF();
</read>
<read>
IF(rd_cmd == `CMD_task_switch_2 && rd_cmdex == `CMDEX_task_switch_2_STEP_13);
SET(rd_req_memory);
ENDIF();
</read>
<read>
IF(rd_cmd == `CMD_task_switch && rd_cmdex >= `CMDEX_task_switch_STEP_12 && rd_cmdex <= `CMDEX_task_switch_STEP_14);
IF(rd_cmdex == `CMDEX_task_switch_STEP_12 && glob_descriptor[`DESC_BITS_TYPE] <= 4'd3); SET(rd_system_linear, glob_desc_base + 32'd12); ENDIF();
IF(rd_cmdex == `CMDEX_task_switch_STEP_12 && glob_descriptor[`DESC_BITS_TYPE] > 4'd3); SET(rd_system_linear, glob_desc_base + 32'h1C); ENDIF();
IF(rd_cmdex == `CMDEX_task_switch_STEP_13 || rd_cmdex == `CMDEX_task_switch_STEP_14); SET(rd_system_linear, rd_task_switch_linear_next); ENDIF();
IF(rd_cmdex != `CMDEX_task_switch_STEP_12 || (glob_descriptor[`DESC_BITS_TYPE] > 4'd3 && cr0_pg));
IF(rd_mutex_busy_memory); SET(rd_waiting);
ELSE();
SET(read_system_dword, glob_descriptor[`DESC_BITS_TYPE] > 4'd3);
SET(read_system_word, glob_descriptor[`DESC_BITS_TYPE] <= 4'd3);
SET(rd_src_is_memory);
IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();
ENDIF();
ENDIF();
ENDIF();
</read>
<read>
IF(rd_cmd == `CMD_task_switch_3);
SET(rd_system_linear, rd_task_switch_linear_next);
IF(rd_cmdex <= `CMDEX_task_switch_3_STEP_12 || glob_descriptor[`DESC_BITS_TYPE] > 4'd3);
SET(read_system_dword, glob_descriptor[`DESC_BITS_TYPE] > 4'd3 && rd_cmdex <= `CMDEX_task_switch_3_STEP_7);
SET(read_system_word, glob_descriptor[`DESC_BITS_TYPE] <= 4'd3 || rd_cmdex > `CMDEX_task_switch_3_STEP_7);
SET(rd_src_is_memory);
IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();
ENDIF();
ENDIF();
</read>
<read>
IF(rd_cmd == `CMD_task_switch_4 && rd_cmdex == `CMDEX_task_switch_4_STEP_0);
SET(rd_system_linear, gdtr_base + { 16'd0, glob_param_1[15:3], 3'd0 } + 32'd4);
IF(rd_mutex_busy_active); SET(rd_waiting); // wait for previous step -- wait for read complete
ELSE();
IF(glob_param_1[`TASK_SWITCH_SOURCE_BITS] != `TASK_SWITCH_FROM_IRET);
SET(read_rmw_system_dword);
SET(rd_src_is_memory);
IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();
ENDIF();
ENDIF();
ENDIF();
</read>
<read>
// load ldt
IF(rd_cmd == `CMD_task_switch_4 && rd_cmdex == `CMDEX_task_switch_4_STEP_2);
IF(rd_mutex_busy_active); SET(rd_waiting); // wait for previous step -- wait for write complete; needed for TLB flush
ELSE();
IF(glob_param_1[`SELECTOR_BIT_TI] == 1'b0 && glob_param_1[15:2] != 14'd0 && ~(rd_descriptor_not_in_limits)); // load null; not in limits
SET(rd_glob_descriptor_set);
SET(rd_glob_descriptor_value, read_8);
SET(rd_glob_param_2_set);
SET(rd_glob_param_2_value, 32'd0);
SET(read_system_descriptor);
IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();
ELSE();
SET(rd_glob_param_2_set);
SET(rd_glob_param_2_value, { 29'd0, glob_param_1[`SELECTOR_BIT_TI], rd_descriptor_not_in_limits, glob_param_1[15:2] == 14'd0 });
ENDIF();
ENDIF();
ENDIF();
</read>
//param_4 used: fs, gs
//param_2 used: control bits
<read>
// load ss,ds,es,fs,gs,cs
IF(rd_cmd == `CMD_task_switch_4 && rd_cmdex >= `CMDEX_task_switch_4_STEP_3 && rd_cmdex <= `CMDEX_task_switch_4_STEP_8);
IF(rd_mutex_busy_active); SET(rd_waiting); // wait for previous step -- wait for write complete for glob_param_1; glob_param_2; write ldt
ELSE();
IF(v8086_mode);
SET(rd_glob_descriptor_set);
SET(rd_glob_descriptor_value, `DESC_MASK_P | `DESC_MASK_DPL | `DESC_MASK_SEG | `DESC_MASK_DATA_RWA | { 24'd0, 4'd0,glob_param_1[15:12], glob_param_1[11:0],4'd0, 16'hFFFF });
SET(rd_glob_param_2_set);
SET(rd_glob_param_2_value, 32'd0);
ELSE();
IF(glob_param_1[15:2] != 14'd0 && ~(rd_descriptor_not_in_limits)); // load null; not in limits
SET(rd_glob_descriptor_set);
SET(rd_glob_descriptor_value, read_8);
SET(rd_glob_param_2_set);
SET(rd_glob_param_2_value, 32'd0);
SET(read_system_descriptor);
IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();
ELSE();
SET(rd_glob_param_2_set);
SET(rd_glob_param_2_value, { 30'd0, rd_descriptor_not_in_limits, glob_param_1[15:2] == 14'd0 });
ENDIF();
ENDIF();
ENDIF();
ENDIF();
</read>
<execute_local>
wire [31:0] exe_new_tss_max;
assign exe_new_tss_max = (glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? 32'h2B : 32'h67;
</execute_local>
<execute>
IF(exe_cmd == `CMD_task_switch && exe_cmdex == `CMDEX_task_switch_STEP_1);
IF(glob_desc_limit < exe_new_tss_max);
SET(exe_waiting);
SET(exe_trigger_ts_fault); //exception TS(val)
SET(exe_error_code, `SELECTOR_FOR_CODE(glob_param_1));
ENDIF();
IF(tr_limit < ((tr_cache[`DESC_BITS_TYPE] <= 4'd3)? 32'h29 : 32'h5F));
SET(exe_waiting);
SET(exe_trigger_ts_fault); //exception TS(val)
SET(exe_error_code, `SELECTOR_FOR_CODE(tr));
ENDIF();
ENDIF();
</execute>
<execute>
IF(exe_cmd == `CMD_task_switch && exe_cmdex == `CMDEX_task_switch_STEP_2);
SET(tlbcheck_do);
SET(tlbcheck_rw, `FALSE);
SET(tlbcheck_address, glob_desc_base);
IF(~(tlbcheck_done) && ~(tlbcheck_page_fault)); SET(exe_waiting); ENDIF();
IF(tlbcheck_page_fault);
SET(exe_waiting);
SET(exe_trigger_pf_fault); //exception PF(val)
ENDIF();
ENDIF();
</execute>
<execute>
IF(exe_cmd == `CMD_task_switch && exe_cmdex == `CMDEX_task_switch_STEP_3);
SET(tlbcheck_do);
SET(tlbcheck_rw, `FALSE);
SET(tlbcheck_address, glob_desc_base + exe_new_tss_max);
IF(~(tlbcheck_done) && ~(tlbcheck_page_fault)); SET(exe_waiting); ENDIF();
IF(tlbcheck_page_fault);
SET(exe_waiting);
SET(exe_trigger_pf_fault); //exception PF(val)
ENDIF();
ENDIF();
</execute>
<execute>
IF(exe_cmd == `CMD_task_switch && exe_cmdex == `CMDEX_task_switch_STEP_4);
SET(tlbcheck_do);
SET(tlbcheck_rw, `TRUE);
SET(tlbcheck_address, glob_desc_base);
IF(~(tlbcheck_done) && ~(tlbcheck_page_fault)); SET(exe_waiting); ENDIF();
IF(tlbcheck_page_fault);
SET(exe_waiting);
SET(exe_trigger_pf_fault); //exception PF(val)
ENDIF();
ENDIF();
</execute>
<execute>
IF(exe_cmd == `CMD_task_switch && exe_cmdex == `CMDEX_task_switch_STEP_5);
SET(tlbcheck_do);
SET(tlbcheck_rw, `TRUE);
SET(tlbcheck_address, glob_desc_base + 32'd1);
IF(~(tlbcheck_done) && ~(tlbcheck_page_fault)); SET(exe_waiting); ENDIF();
IF(tlbcheck_page_fault);
SET(exe_waiting);
SET(exe_trigger_pf_fault); //exception PF(val)
ENDIF();
ENDIF();
</execute>
<execute>
IF(exe_cmd == `CMD_task_switch && exe_cmdex == `CMDEX_task_switch_STEP_7);
SET(tlbcheck_do);
SET(tlbcheck_rw, `TRUE);
SET(tlbcheck_address, (tr_cache[`DESC_BITS_TYPE] <= 4'd3)? tr_base + 32'd14 : tr_base + 32'h20);
IF(~(tlbcheck_done) && ~(tlbcheck_page_fault)); SET(exe_waiting); ENDIF();
IF(tlbcheck_page_fault);
SET(exe_waiting);
SET(exe_trigger_pf_fault); //exception PF(val)
ENDIF();
ENDIF();
</execute>
<execute>
IF(exe_cmd == `CMD_task_switch && exe_cmdex == `CMDEX_task_switch_STEP_8);
SET(tlbcheck_do);
SET(tlbcheck_rw, `TRUE);
SET(tlbcheck_address, (tr_cache[`DESC_BITS_TYPE] <= 4'd3)? tr_base + 32'd41 : tr_base + 32'h5D);
IF(~(tlbcheck_done) && ~(tlbcheck_page_fault)); SET(exe_waiting); ENDIF();
IF(tlbcheck_page_fault);
SET(exe_waiting);
SET(exe_trigger_pf_fault); //exception PF(val)
ENDIF();
ENDIF();
</execute>
<execute>
IF(exe_cmd == `CMD_task_switch && exe_cmdex == `CMDEX_task_switch_STEP_10);
SET(exe_result_push, exe_push_eflags);
ENDIF();
</execute>
<execute>
IF(exe_cmd == `CMD_task_switch && exe_cmdex >= `CMDEX_task_switch_STEP_12 && exe_cmdex <= `CMDEX_task_switch_STEP_14);
IF(exe_ready);
SAVE(exe_buffer, src);
SET(exe_buffer_shift);
ENDIF();
ENDIF();
</execute>
<execute>
IF(exe_cmd == `CMD_task_switch_2);
IF(exe_cmdex <= `CMDEX_task_switch_2_STEP_7);
SET(exe_result2, src);
ENDIF();
IF(exe_cmdex > `CMDEX_task_switch_2_STEP_7);
SET(exe_result2, { 16'd0, e_seg_by_cmdex });
ENDIF();
ENDIF();
</execute>
<execute>
IF(exe_cmd == `CMD_task_switch_3);
IF(exe_ready);
SAVE(exe_buffer, (exe_cmdex == `CMDEX_task_switch_3_STEP_15 && glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? 32'd0 : src);
SET(exe_buffer_shift, exe_cmdex <= `CMDEX_task_switch_3_STEP_8);
SET(exe_buffer_shift_word, exe_cmdex > `CMDEX_task_switch_3_STEP_8);
ENDIF();
ENDIF();
</execute>
<execute>
IF(exe_cmd == `CMD_task_switch_4 && exe_cmdex == `CMDEX_task_switch_4_STEP_0);
SET(exe_result2, src);
ENDIF();
</execute>
<execute>
IF(exe_cmd == `CMD_task_switch_4 && exe_cmdex == `CMDEX_task_switch_4_STEP_2);
IF(glob_param_2[2] || glob_param_2[2:0] == 3'b010 || (
glob_param_2[2:0] == 3'b000 && (
exe_descriptor[`DESC_BIT_SEG] ||
exe_descriptor[`DESC_BITS_TYPE] != `DESC_LDT ||
exe_descriptor[`DESC_BIT_P] == `FALSE
)
));
SET(exe_waiting);
SET(exe_trigger_ts_fault);
SET(exe_error_code, `SELECTOR_FOR_CODE(glob_param_1));
ENDIF();
ENDIF();
</execute>
<execute>
// load ss
IF(exe_cmd == `CMD_task_switch_4 && exe_cmdex == `CMDEX_task_switch_4_STEP_3);
IF(~(v8086_mode));
IF(glob_param_2[1:0] != 2'b00 || (
exe_descriptor[`DESC_BIT_SEG] == 1'b0 ||
`DESC_IS_CODE(exe_descriptor) ||
`DESC_IS_DATA_RO(exe_descriptor) ||
(exe_descriptor[`DESC_BIT_P] && (
exe_descriptor[`DESC_BITS_DPL] != wr_task_rpl ||
exe_descriptor[`DESC_BITS_DPL] != exe_selector[`SELECTOR_BITS_RPL]
)
)
));
SET(exe_waiting);
SET(exe_trigger_ts_fault);
SET(exe_error_code, `SELECTOR_FOR_CODE(glob_param_1));
ENDIF();
IF(glob_param_2[1:0] == 2'b00 && exe_descriptor[`DESC_BIT_SEG] && `DESC_IS_DATA_RW(exe_descriptor) && ~(exe_descriptor[`DESC_BIT_P]));
SET(exe_waiting);
SET(exe_trigger_ss_fault);
SET(exe_error_code, `SELECTOR_FOR_CODE(glob_param_1));
ENDIF();
ENDIF();
ENDIF();
</execute>
<execute>
// load ds,es,fs,gs
IF(exe_cmd == `CMD_task_switch_4 && exe_cmdex >= `CMDEX_task_switch_4_STEP_4 && exe_cmdex <= `CMDEX_task_switch_4_STEP_7);
IF(~(v8086_mode));
IF(glob_param_2[1:0] == 2'b10 || (glob_param_2[1:0] == 2'b00 && (
exe_descriptor[`DESC_BIT_SEG] == 1'b0 ||
`DESC_IS_CODE_EO(exe_descriptor) ||
((`DESC_IS_DATA(exe_descriptor) || `DESC_IS_CODE_NON_CONFORMING(exe_descriptor)) && exe_privilege_not_accepted)
)));
SET(exe_waiting);
SET(exe_trigger_ts_fault);
SET(exe_error_code, `SELECTOR_FOR_CODE(glob_param_1));
ENDIF();
IF(glob_param_2[1:0] == 2'b00 && ~(exe_trigger_ts_fault) && ~(exe_descriptor[`DESC_BIT_P]));
SET(exe_waiting);
SET(exe_trigger_np_fault);
SET(exe_error_code, `SELECTOR_FOR_CODE(glob_param_1));
ENDIF();
ENDIF();
ENDIF();
</execute>
<execute>
// load cs
IF(exe_cmd == `CMD_task_switch_4 && exe_cmdex == `CMDEX_task_switch_4_STEP_8);
IF(~(v8086_mode));
IF(glob_param_2[1:0] != 2'b00 || (
exe_descriptor[`DESC_BIT_SEG] == 1'b0 ||
`DESC_IS_DATA(exe_descriptor) ||
(`DESC_IS_CODE_NON_CONFORMING(exe_descriptor) && exe_descriptor[`DESC_BITS_DPL] != exe_selector[`SELECTOR_BITS_RPL]) ||
(`DESC_IS_CODE_CONFORMING(exe_descriptor) && exe_descriptor[`DESC_BITS_DPL] > exe_selector[`SELECTOR_BITS_RPL])
));
SET(exe_waiting);
SET(exe_trigger_ts_fault);
SET(exe_error_code, `SELECTOR_FOR_CODE(glob_param_1));
ENDIF();
IF(glob_param_2[1:0] == 2'b00 && ~(exe_trigger_ts_fault) && ~(exe_descriptor[`DESC_BIT_P]));
SET(exe_waiting);
SET(exe_trigger_np_fault);
SET(exe_error_code, `SELECTOR_FOR_CODE(glob_param_1));
ENDIF();
ENDIF();
ENDIF();
</execute>
<execute>
IF(exe_cmd == `CMD_task_switch_4 && exe_cmdex == `CMDEX_task_switch_4_STEP_9);
SET(offset_task);
SET(exe_result_push, { 16'd0, glob_param_3[15:0] });
ENDIF();
</execute>
<execute>
// check eip
IF(exe_cmd == `CMD_task_switch_4 && exe_cmdex == `CMDEX_task_switch_4_STEP_10);
SET(exe_glob_param_2_set);
SET(exe_glob_param_2_value, exe_eip);
SET(exe_eip_from_glob_param_2);
SET(exe_task_switch_finished);
IF(exe_eip > cs_limit);
SET(exe_waiting);
SET(exe_trigger_gp_fault); //exception GP(0)
ENDIF();
ENDIF();
</execute>
<write_local>
wire [31:0] wr_task_switch_linear;
wire [31:0] wr_task_switch_linear_next;
reg [31:0] wr_task_switch_linear_reg;
assign wr_task_switch_linear =
(wr_cmd == `CMD_task_switch && wr_cmdex == `CMDEX_task_switch_STEP_9 && tr_cache[`DESC_BITS_TYPE] <= 4'd3)? tr_base + 32'd14 :
(wr_cmd == `CMD_task_switch && wr_cmdex == `CMDEX_task_switch_STEP_9 && tr_cache[`DESC_BITS_TYPE] > 4'd3)? tr_base + 32'h20 :
wr_task_switch_linear_next;
assign wr_task_switch_linear_next =
(tr_cache[`DESC_BITS_TYPE] <= 4'd3)? wr_task_switch_linear_reg + 32'd2 :
wr_task_switch_linear_reg + 32'd4;
always @(posedge clk or negedge rst_n) begin
if(rst_n == 1'b0) wr_task_switch_linear_reg <= 32'd0;
else if(wr_cmd == `CMD_task_switch && wr_cmdex == `CMDEX_task_switch_STEP_9) wr_task_switch_linear_reg <= wr_task_switch_linear;
else if(wr_ready) wr_task_switch_linear_reg <= wr_task_switch_linear_next;
end
</write_local>
<write>
IF(wr_cmd == `CMD_task_switch && wr_cmdex == `CMDEX_task_switch_STEP_1);
SET(wr_debug_trap_clear);
SET(wr_not_finished);
ENDIF();
</write>
<write>
IF(wr_cmd == `CMD_task_switch && (wr_cmdex == `CMDEX_task_switch_STEP_2 || wr_cmdex == `CMDEX_task_switch_STEP_3 || wr_cmdex == `CMDEX_task_switch_STEP_4 || wr_cmdex == `CMDEX_task_switch_STEP_5));
SET(wr_not_finished);
ENDIF();
</write>
<write>
IF(wr_cmd == `CMD_task_switch && wr_cmdex == `CMDEX_task_switch_STEP_6);
SET(wr_not_finished);
IF(glob_param_1[`TASK_SWITCH_SOURCE_BITS] == `TASK_SWITCH_FROM_JUMP || glob_param_1[`TASK_SWITCH_SOURCE_BITS] == `TASK_SWITCH_FROM_IRET);
SET(wr_system_dword, glob_param_2 & 32'hFFFFFDFF);
SET(write_rmw_system_dword);
IF(~(write_for_wr_ready)); SET(wr_waiting); ENDIF();
ENDIF();
ENDIF();
</write>
<write>
IF(wr_cmd == `CMD_task_switch && (wr_cmdex == `CMDEX_task_switch_STEP_7 || wr_cmdex == `CMDEX_task_switch_STEP_8));
SET(wr_not_finished);
ENDIF();
</write>
<write>
IF(wr_cmd == `CMD_task_switch && wr_cmdex == `CMDEX_task_switch_STEP_9);
SET(wr_not_finished);
SET(wr_system_dword, (glob_param_1[`TASK_SWITCH_SOURCE_BITS] == `TASK_SWITCH_FROM_INT)? exc_eip : eip);
SET(wr_system_linear, wr_task_switch_linear);
SET(write_system_word, tr_cache[`DESC_BITS_TYPE] <= 4'd3);
SET(write_system_dword, tr_cache[`DESC_BITS_TYPE] > 4'd3);
IF(~(write_for_wr_ready)); SET(wr_waiting); ENDIF();
ENDIF();
</write>
<write>
IF(wr_cmd == `CMD_task_switch && wr_cmdex == `CMDEX_task_switch_STEP_10);
SET(wr_not_finished);
SET(wr_system_dword, result_push &
((glob_descriptor[`DESC_BITS_TYPE] == `DESC_TSS_BUSY_286 || glob_descriptor[`DESC_BITS_TYPE] == `DESC_TSS_BUSY_386)? 32'hFFFFBFFF : 32'hFFFFFFFF));
SET(wr_system_linear, wr_task_switch_linear);
SET(write_system_word, tr_cache[`DESC_BITS_TYPE] <= 4'd3);
SET(write_system_dword, tr_cache[`DESC_BITS_TYPE] > 4'd3);
IF(~(write_for_wr_ready)); SET(wr_waiting); ENDIF();
ENDIF();
</write>
<write>
IF(wr_cmd == `CMD_task_switch_2 && wr_cmdex <= `CMDEX_task_switch_2_STEP_13);
SET(wr_not_finished);
IF(tr_cache[`DESC_BITS_TYPE] > 4'd3 || wr_cmdex <= `CMDEX_task_switch_2_STEP_11);
SET(wr_system_dword, result2);
SET(wr_system_linear, wr_task_switch_linear);
SET(write_system_word, tr_cache[`DESC_BITS_TYPE] <= 4'd3 || wr_cmdex > `CMDEX_task_switch_2_STEP_7);
SET(write_system_dword, tr_cache[`DESC_BITS_TYPE] > 4'd3 && wr_cmdex <= `CMDEX_task_switch_2_STEP_7);
IF(~(write_for_wr_ready)); SET(wr_waiting); ENDIF();
ENDIF();
ENDIF();
</write>
<write>
IF(wr_cmd == `CMD_task_switch && wr_cmdex == `CMDEX_task_switch_STEP_11);
SET(wr_not_finished);
IF(glob_param_1[`TASK_SWITCH_SOURCE_BITS] == `TASK_SWITCH_FROM_CALL || glob_param_1[`TASK_SWITCH_SOURCE_BITS] == `TASK_SWITCH_FROM_INT);
SET(wr_system_dword, { 16'd0, tr });
SET(wr_system_linear, glob_desc_base);
SET(write_system_word);
IF(~(write_for_wr_ready)); SET(wr_waiting); ENDIF();
ENDIF();
ENDIF();
</write>
<write>
IF(wr_cmd == `CMD_task_switch && wr_cmdex >= `CMDEX_task_switch_STEP_12 && wr_cmdex <= `CMDEX_task_switch_STEP_14);
SET(wr_not_finished);
ENDIF();
</write>
<write>
IF(wr_cmd == `CMD_task_switch_3);
SET(wr_not_finished);
ENDIF();
</write>
<write>
IF(wr_cmd == `CMD_task_switch_4 && wr_cmdex == `CMDEX_task_switch_4_STEP_0);
SET(wr_not_finished);
IF(glob_param_1[`TASK_SWITCH_SOURCE_BITS] != `TASK_SWITCH_FROM_IRET);
SET(wr_system_dword, result2 | 32'h00000200);
SET(write_rmw_system_dword);
IF(~(write_for_wr_ready)); SET(wr_waiting); ENDIF();
ENDIF();
ENDIF();
</write>
<write>
IF(wr_cmd == `CMD_task_switch_4 && wr_cmdex == `CMDEX_task_switch_4_STEP_1);
SET(wr_not_finished);
SET(wr_make_esp_commit);
SET(wr_glob_param_1_set);
SET(wr_glob_param_1_value, (glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? { 13'd0, `SEGMENT_LDT, exe_buffer_shifted[47:32] } : { 13'd0, `SEGMENT_LDT, exe_buffer_shifted[15:0] });
SET(wr_glob_param_3_set);
SET(wr_glob_param_3_value, (glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? glob_param_3 : glob_param_3 | 32'h00020000); //bit 17: [internal] is push 32 bit (TSS386)
SET(wr_glob_param_4_set);
SET(wr_glob_param_4_value, { task_fs, task_gs });
SAVE(eax, (glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? { 16'hFFFF, exe_buffer_shifted[351:336] } : exe_buffer_shifted[367:336]);
SAVE(ecx, (glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? { 16'hFFFF, exe_buffer_shifted[319:304] } : exe_buffer_shifted[335:304]);
SAVE(edx, (glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? { 16'hFFFF, exe_buffer_shifted[287:272] } : exe_buffer_shifted[303:272]);
SAVE(ebx, (glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? { 16'hFFFF, exe_buffer_shifted[255:240] } : exe_buffer_shifted[271:240]);
SAVE(esp, (glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? { 16'hFFFF, exe_buffer_shifted[223:208] } : exe_buffer_shifted[239:208]);
SAVE(ebp, (glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? { 16'hFFFF, exe_buffer_shifted[191:176] } : exe_buffer_shifted[207:176]);
SAVE(esi, (glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? { 16'hFFFF, exe_buffer_shifted[159:144] } : exe_buffer_shifted[175:144]);
SAVE(edi, (glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? { 16'hFFFF, exe_buffer_shifted[127:112] } : exe_buffer_shifted[143:112]);
SAVE(cflag, task_eflags[0]);
SAVE(pflag, task_eflags[2]);
SAVE(aflag, task_eflags[4]);
SAVE(zflag, task_eflags[6]);
SAVE(sflag, task_eflags[7]);
SAVE(tflag, task_eflags[8]);
SAVE(iflag, task_eflags[9]);
SAVE(dflag, task_eflags[10]);
SAVE(oflag, task_eflags[11]);
SAVE(iopl, task_eflags[13:12]);
SAVE(ntflag, task_eflags[14] | +
(glob_param_1[`TASK_SWITCH_SOURCE_BITS] == `TASK_SWITCH_FROM_CALL || glob_param_1[`TASK_SWITCH_SOURCE_BITS] == `TASK_SWITCH_FROM_INT));
SAVE(rflag, task_eflags[16]);
SAVE(vmflag, task_eflags[17]);
SAVE(acflag, task_eflags[18]);
SAVE(idflag, task_eflags[21]);
SAVE(dr7, dr7 & 32'hFFFFFEAA);
SAVE(cr0_ts, `TRUE);
//set tr, tr_cache, tr_cache.type |= 2 -- set busy
SAVE(tr, glob_param_1[15:0]);
SAVE(tr_rpl, glob_param_1[1:0]);
SAVE(tr_cache, glob_descriptor | 64'h0000020000000000);
//set selectors, cache valid: 6+ldt
SAVE(cs, task_cs);
SAVE(cs_cache_valid, `FALSE);
SAVE(cs_rpl, 2'd3);
SAVE(wr_task_rpl, task_cs[1:0]);
SAVE(ds, task_ds);
SAVE(ds_cache_valid, `FALSE);
SAVE(ds_rpl, task_ds[1:0]);
SAVE(es, task_es);
SAVE(es_cache_valid, `FALSE);
SAVE(es_rpl, task_es[1:0]);
SAVE(fs, task_fs);
SAVE(fs_cache_valid, `FALSE);
SAVE(fs_rpl, task_fs[1:0]);
SAVE(gs, task_gs);
SAVE(gs_cache_valid, `FALSE);
SAVE(gs_rpl, task_gs[1:0]);
SAVE(ss, task_ss);
SAVE(ss_cache_valid, `FALSE);
SAVE(ss_rpl, task_ss[1:0]);
SAVE(ldtr, task_ldtr);
SAVE(ldtr_cache_valid, `FALSE);
SAVE(ldtr_rpl, task_ldtr[1:0]);
IF(glob_descriptor[`DESC_BITS_TYPE] >= 4'd9 && cr0_pg && cr3 != exe_buffer_shifted[463:432]);
SAVE(cr3, exe_buffer_shifted[463:432]);
SET(tlbflushall_do);
ENDIF();
ENDIF();
</write>
<write>
IF(wr_cmd == `CMD_task_switch_4 && wr_cmdex == `CMDEX_task_switch_4_STEP_2);
SET(wr_not_finished);
SET(wr_glob_param_1_set);
SET(wr_glob_param_1_value, { 13'd0, `SEGMENT_SS, task_ss });
IF(glob_param_2[2:0] == 3'b000);
SAVE(ldtr_cache, glob_descriptor);
SAVE(ldtr_cache_valid, `TRUE);
ENDIF();
ENDIF();
</write>
<write>
IF(wr_cmd == `CMD_task_switch_4 && wr_cmdex >= `CMDEX_task_switch_4_STEP_3 && wr_cmdex <= `CMDEX_task_switch_4_STEP_8);
SET(wr_not_finished);
IF(wr_cmdex == `CMDEX_task_switch_4_STEP_3); SAVE(cs_rpl, wr_task_rpl); ENDIF();
IF(glob_param_2[1:0] == 2'b00 && ~(v8086_mode) && `DESC_IS_NOT_ACCESSED(glob_descriptor));
SET(write_system_touch);
IF(~(write_for_wr_ready)); SET(wr_waiting);
ELSE();
IF(wr_cmdex == `CMDEX_task_switch_4_STEP_3);
SET(wr_glob_param_1_set);
SET(wr_glob_param_1_value, { 13'd0, `SEGMENT_DS, task_ds });
ENDIF();
IF(wr_cmdex == `CMDEX_task_switch_4_STEP_4);
SET(wr_glob_param_1_set);
SET(wr_glob_param_1_value, { 13'd0, `SEGMENT_ES, task_es });
ENDIF();
IF(wr_cmdex == `CMDEX_task_switch_4_STEP_5);
SET(wr_glob_param_1_set);
SET(wr_glob_param_1_value, { 13'd0, `SEGMENT_FS, glob_param_4[31:16] });
ENDIF();
IF(wr_cmdex == `CMDEX_task_switch_4_STEP_6);
SET(wr_glob_param_1_set);
SET(wr_glob_param_1_value, { 13'd0, `SEGMENT_GS, glob_param_4[15:0] });
ENDIF();
IF(wr_cmdex == `CMDEX_task_switch_4_STEP_7);
SET(wr_glob_param_1_set);
SET(wr_glob_param_1_value, { 13'd0, `SEGMENT_CS, task_cs });
ENDIF();
SET(wr_seg_cache_valid, `TRUE);
SET(write_seg_cache_valid);
SET(write_seg_cache);
ENDIF();
ENDIF();
IF(glob_param_2[1:0] == 2'b00 && `DESC_IS_ACCESSED(glob_descriptor));
IF(wr_cmdex == `CMDEX_task_switch_4_STEP_3);
SET(wr_glob_param_1_set);
SET(wr_glob_param_1_value, { 13'd0, `SEGMENT_DS, task_ds });
ENDIF();
IF(wr_cmdex == `CMDEX_task_switch_4_STEP_4);
SET(wr_glob_param_1_set);
SET(wr_glob_param_1_value, { 13'd0, `SEGMENT_ES, task_es });
ENDIF();
IF(wr_cmdex == `CMDEX_task_switch_4_STEP_5);
SET(wr_glob_param_1_set);
SET(wr_glob_param_1_value, { 13'd0, `SEGMENT_FS, glob_param_4[31:16] });
ENDIF();
IF(wr_cmdex == `CMDEX_task_switch_4_STEP_6);
SET(wr_glob_param_1_set);
SET(wr_glob_param_1_value, { 13'd0, `SEGMENT_GS, glob_param_4[15:0] });
ENDIF();
IF(wr_cmdex == `CMDEX_task_switch_4_STEP_7);
SET(wr_glob_param_1_set);
SET(wr_glob_param_1_value, { 13'd0, `SEGMENT_CS, task_cs });
ENDIF();
SET(wr_seg_sel, glob_param_1[15:0]);
SET(wr_seg_cache_valid, `TRUE);
SET(write_seg_cache_valid);
SET(write_seg_cache);
IF(v8086_mode);
SET(wr_seg_rpl, 2'd3);
SET(write_seg_rpl);
ENDIF();
ENDIF();
IF(glob_param_2[1:0] != 2'b00);
IF(wr_cmdex == `CMDEX_task_switch_4_STEP_3);
SET(wr_glob_param_1_set);
SET(wr_glob_param_1_value, { 13'd0, `SEGMENT_DS, task_ds });
ENDIF();
IF(wr_cmdex == `CMDEX_task_switch_4_STEP_4);
SET(wr_glob_param_1_set);
SET(wr_glob_param_1_value, { 13'd0, `SEGMENT_ES, task_es });
ENDIF();
IF(wr_cmdex == `CMDEX_task_switch_4_STEP_5);
SET(wr_glob_param_1_set);
SET(wr_glob_param_1_value, { 13'd0, `SEGMENT_FS, glob_param_4[31:16] });
ENDIF();
IF(wr_cmdex == `CMDEX_task_switch_4_STEP_6);
SET(wr_glob_param_1_set);
SET(wr_glob_param_1_value, { 13'd0, `SEGMENT_GS, glob_param_4[15:0] });
ENDIF();
IF(wr_cmdex == `CMDEX_task_switch_4_STEP_7);
SET(wr_glob_param_1_set);
SET(wr_glob_param_1_value, { 13'd0, `SEGMENT_CS, task_cs });
ENDIF();
ENDIF();
ENDIF();
</write>
<write>
IF(wr_cmd == `CMD_task_switch_4 && wr_cmdex == `CMDEX_task_switch_4_STEP_9);
SET(wr_not_finished);
SET(wr_push_length_word, ~(glob_param_3[17]));
SET(wr_push_length_dword, glob_param_3[17]);
IF(glob_param_3[16]); // push error code
SET(wr_push_ss_fault_check);
SET(wr_one_cycle_wait);
SET(wr_make_esp_speculative);
IF(~(write_for_wr_ready)); SET(wr_waiting); ENDIF();
IF(~(wr_push_ss_fault));
SAVE(esp, wr_stack_esp);
SET(write_stack_virtual);
ENDIF();
ENDIF();
ENDIF();
</write>
<write>
IF(wr_cmd == `CMD_task_switch_4 && wr_cmdex == `CMDEX_task_switch_4_STEP_10);
SET(wr_make_esp_commit);
// finish exception/interrupt
SET(wr_exception_finished);
IF(glob_param_3[17] && task_trap[0]); SET(wr_debug_task_trigger); ENDIF();
// clear pipeline
SET(wr_req_reset_pr);
SET(wr_req_reset_dec);
SET(wr_req_reset_micro);
SET(wr_req_reset_rd);
SET(wr_req_reset_exe);
ENDIF();
</write>
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