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# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
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# Copyright (C) 1991-2013 Altera Corporation
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# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
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# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
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# Clock constraints

create_clock -name "CLOCK_50" -period 20.000ns [get_ports {CLOCK_50}]


# Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks

# Automatically calculate clock uncertainty to jitter and other effects.
derive_clock_uncertainty

# tsu/th constraints

# tco constraints

# tpd constraints