URL
https://opencores.org/ocsvn/ao486/ao486/trunk
Subversion Repositories ao486
[/] [ao486/] [trunk/] [syn/] [soc/] [soc_assignment_defaults.qdf] - Rev 8
Go to most recent revision | Compare with Previous | Blame | View Log
# -------------------------------------------------------------------------- ### Copyright (C) 1991-2013 Altera Corporation# Your use of Altera Corporation's design tools, logic functions# and other software and tools, and its AMPP partner logic# functions, and any output files from any of the foregoing# (including device programming or simulation files), and any# associated documentation or information are expressly subject# to the terms and conditions of the Altera Program License# Subscription Agreement, Altera MegaCore Function License# Agreement, or other applicable license agreement, including,# without limitation, that your use is for the sole purpose of# programming logic devices manufactured by Altera and sold by# Altera or its authorized distributors. Please refer to the# applicable agreement for further details.## -------------------------------------------------------------------------- ### Quartus II 64-Bit# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition# Date created = 23:26:50 November 05, 2013## -------------------------------------------------------------------------- ### Note:## 1) Do not modify this file. This file was generated# automatically by the Quartus II software and is used# to preserve global assignments across Quartus II versions.## -------------------------------------------------------------------------- #set_global_assignment -name PROJECT_SHOW_ENTITY_NAME Onset_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Offset_global_assignment -name VER_COMPATIBLE_DB_DIR export_dbset_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Offset_global_assignment -name SMART_RECOMPILE Offset_global_assignment -name FLOW_DISABLE_ASSEMBLER Offset_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Offset_global_assignment -name FLOW_ENABLE_HC_COMPARE Offset_global_assignment -name HC_OUTPUT_DIR hc_outputset_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Offset_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Offset_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE Onset_global_assignment -name FLOW_ENABLE_RTL_VIEWER Offset_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK Onset_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES Onset_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Offset_global_assignment -name REVISION_TYPE Baseset_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS Onset_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS Onset_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK Onset_global_assignment -name DO_COMBINED_ANALYSIS Offset_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Onset_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Offset_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS Onset_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS Onset_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V"set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV"set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E"set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III"set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX V"set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix V"set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V GZ"set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II"set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX"set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GZ"set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III LS"set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix III"set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone V"set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Offset_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III"set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III LS"set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix III"set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V"set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E"set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV"set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III"set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX V"set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix V"set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V GZ"set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II"set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX"set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GZ"set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX"set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III LS"set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix III"set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone V"set_global_assignment -name MUX_RESTRUCTURE Autoset_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Offset_global_assignment -name ENABLE_IP_DEBUG Offset_global_assignment -name SAVE_DISK_SPACE Onset_global_assignment -name DISABLE_OCP_HW_EVAL Offset_global_assignment -name DEVICE_FILTER_PACKAGE Anyset_global_assignment -name DEVICE_FILTER_PIN_COUNT Anyset_global_assignment -name DEVICE_FILTER_SPEED_GRADE Anyset_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993set_global_assignment -name FAMILY "Cyclone IV GX"set_global_assignment -name TRUE_WYSIWYG_FLOW Offset_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Offset_global_assignment -name STATE_MACHINE_PROCESSING Autoset_global_assignment -name SAFE_STATE_MACHINE Offset_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES Onset_global_assignment -name EXTRACT_VHDL_STATE_MACHINES Onset_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Offset_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC Onset_global_assignment -name PARALLEL_SYNTHESIS Onset_global_assignment -name DSP_BLOCK_BALANCING Autoset_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"set_global_assignment -name NOT_GATE_PUSH_BACK Onset_global_assignment -name ALLOW_POWER_UP_DONT_CARE Onset_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Offset_global_assignment -name REMOVE_DUPLICATE_REGISTERS Onset_global_assignment -name IGNORE_CARRY_BUFFERS Offset_global_assignment -name IGNORE_CASCADE_BUFFERS Offset_global_assignment -name IGNORE_GLOBAL_BUFFERS Offset_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Offset_global_assignment -name IGNORE_LCELL_BUFFERS Offset_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTOset_global_assignment -name IGNORE_SOFT_BUFFERS Onset_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Offset_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Offset_global_assignment -name AUTO_GLOBAL_CLOCK_MAX Onset_global_assignment -name AUTO_GLOBAL_OE_MAX Onset_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS Onset_global_assignment -name AUTO_IMPLEMENT_IN_ROM Offset_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lutset_global_assignment -name OPTIMIZATION_TECHNIQUE Balancedset_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balancedset_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balancedset_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balancedset_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balancedset_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balancedset_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speedset_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balancedset_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Areaset_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Areaset_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Areaset_global_assignment -name ALLOW_XOR_GATE_USAGE Onset_global_assignment -name AUTO_LCELL_INSERTION Onset_global_assignment -name CARRY_CHAIN_LENGTH 48set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70set_global_assignment -name CASCADE_CHAIN_LENGTH 2set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4set_global_assignment -name AUTO_CARRY_CHAINS Onset_global_assignment -name AUTO_CASCADE_CHAINS Onset_global_assignment -name AUTO_PARALLEL_EXPANDERS Onset_global_assignment -name AUTO_OPEN_DRAIN_PINS Onset_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Offset_global_assignment -name AUTO_ROM_RECOGNITION Onset_global_assignment -name AUTO_RAM_RECOGNITION Onset_global_assignment -name AUTO_DSP_RECOGNITION Onset_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Autoset_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Autoset_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION Onset_global_assignment -name STRICT_RAM_RECOGNITION Offset_global_assignment -name ALLOW_SYNCH_CTRL_USAGE Onset_global_assignment -name FORCE_SYNCH_CLEAR Offset_global_assignment -name AUTO_RAM_BLOCK_BALANCING Onset_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Offset_global_assignment -name AUTO_RESOURCE_SHARING Offset_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Offset_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Offset_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Offset_global_assignment -name MAX7000_FANIN_PER_CELL 100set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING Onset_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Offset_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Offset_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone III LS"set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone III"set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix III"set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"set_global_assignment -name REPORT_PARAMETER_SETTINGS Onset_global_assignment -name REPORT_SOURCE_ASSIGNMENTS Onset_global_assignment -name REPORT_CONNECTIVITY_CHECKS Onset_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Offset_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone III"set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone III LS"set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix III"set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"set_global_assignment -name HDL_MESSAGE_LEVEL Level2set_global_assignment -name USE_HIGH_SPEED_ADDER Autoset_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION Onset_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Offset_global_assignment -name BLOCK_DESIGN_NAMING Autoset_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Offset_global_assignment -name SYNTHESIS_EFFORT Autoset_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL Onset_global_assignment -name PRE_MAPPING_RESYNTHESIS Offset_global_assignment -name SYNTH_MESSAGE_LEVEL Mediumset_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Autoset_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III LS"set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III"set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix III"set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"set_global_assignment -name MAX_LABS "-1 (Unlimited)"set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR Onset_global_assignment -name SYNTHESIS_SEED 1set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"set_global_assignment -name AUTO_PARALLEL_SYNTHESIS Onset_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Offset_global_assignment -name AUTO_MERGE_PLLS Onset_global_assignment -name IGNORE_MODE_FOR_MERGE Offset_global_assignment -name TXPMA_SLEW_RATE Lowset_global_assignment -name ADCE_ENABLED Autoset_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normalset_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Offset_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Offset_global_assignment -name DEVICE AUTOset_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Offset_global_assignment -name ENABLE_JTAG_BST_SUPPORT Offset_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT Onset_global_assignment -name ENABLE_NCEO_OUTPUT Offset_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"set_global_assignment -name STRATIXIII_UPDATE_MODE Standardset_global_assignment -name STRATIX_UPDATE_MODE Standardset_global_assignment -name INTERNAL_FLASH_UPDATE_MODE Standardset_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Offset_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 00000000set_global_assignment -name CVP_MODE Offset_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial"set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"set_global_assignment -name USER_START_UP_CLOCK Offset_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSCset_global_assignment -name ENABLE_VREFA_PIN Offset_global_assignment -name ENABLE_VREFB_PIN Offset_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Offset_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Offset_global_assignment -name ENABLE_DEVICE_WIDE_RESET Offset_global_assignment -name ENABLE_DEVICE_WIDE_OE Offset_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Offset_global_assignment -name INIT_DONE_OPEN_DRAIN Onset_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"set_global_assignment -name ENABLE_CONFIGURATION_PINS Onset_global_assignment -name ENABLE_JTAG_PIN_SHARING Offset_global_assignment -name ENABLE_NCE_PIN Onset_global_assignment -name ENABLE_BOOT_SEL_PIN Onset_global_assignment -name CRC_ERROR_CHECKING Offset_global_assignment -name INTERNAL_SCRUBBING Offset_global_assignment -name PR_ERROR_OPEN_DRAIN Onset_global_assignment -name PR_READY_OPEN_DRAIN Onset_global_assignment -name ENABLE_CVP_CONFDONE Offset_global_assignment -name CVP_CONFDONE_OPEN_DRAIN Onset_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III LS"set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III"set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix III"set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone III"set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone III LS"set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix III"set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION Onset_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Autoset_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Careset_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automaticset_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME Onset_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"set_global_assignment -name OPTIMIZE_SSN Offset_global_assignment -name OPTIMIZE_TIMING "Normal compilation"set_global_assignment -name ECO_OPTIMIZE_TIMING Offset_global_assignment -name ECO_REGENERATE_REPORT Offset_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normalset_global_assignment -name FIT_ONLY_ONE_ATTEMPT Offset_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automaticallyset_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automaticallyset_global_assignment -name SEED 1set_global_assignment -name SLOW_SLEW_RATE Offset_global_assignment -name PCI_IO Offset_global_assignment -name VREF_MODE EXTERNALset_global_assignment -name TURBO_BIT Onset_global_assignment -name WEAK_PULL_UP_RESISTOR Offset_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Offset_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Offset_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES Onset_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTOset_global_assignment -name AUTO_PACKED_REGISTERS_MAXII AUTOset_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE Autoset_global_assignment -name AUTO_PACKED_REGISTERS Offset_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX AUTOset_global_assignment -name NORMAL_LCELL_INSERT Onset_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT Onset_global_assignment -name AUTO_DELAY_CHAINS Onset_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFFset_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Offset_global_assignment -name TREAT_BIDIR_AS_OUTPUT Offset_global_assignment -name AUTO_TURBO_BIT ONset_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Offset_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Offset_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Offset_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Offset_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Offset_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Offset_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Offset_global_assignment -name IO_PLACEMENT_OPTIMIZATION Onset_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Offset_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Offset_global_assignment -name FITTER_EFFORT "Auto Fit"set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0nsset_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normalset_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTOset_global_assignment -name ROUTER_REGISTER_DUPLICATION AUTOset_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Offset_global_assignment -name AUTO_GLOBAL_CLOCK Onset_global_assignment -name AUTO_GLOBAL_OE Onset_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS Onset_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realisticset_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Offset_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Offset_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Offset_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Offset_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Offset_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Offset_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Offset_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Offset_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Offset_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Offset_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Offset_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Offset_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Offset_global_assignment -name GENERATE_GXB_RECONFIG_MIF Offset_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Offset_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"set_global_assignment -name ENABLE_HOLD_BACK_OFF Onset_global_assignment -name CONFIGURATION_VCCIO_LEVEL Autoset_global_assignment -name FORCE_CONFIGURATION_VCCIO Offset_global_assignment -name SYNCHRONIZER_IDENTIFICATION Offset_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION Onset_global_assignment -name OPTIMIZE_FOR_METASTABILITY Onset_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III"set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III LS"set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Stratix III"set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"set_global_assignment -name MAX_LARGE_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Offset_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY Onset_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Offset_global_assignment -name AUTO_C3_M9K_BIT_SKIP Offset_global_assignment -name PR_DONE_OPEN_DRAIN Onset_global_assignment -name NCEO_OPEN_DRAIN Onset_global_assignment -name ENABLE_CRC_ERROR_PIN Offset_global_assignment -name ENABLE_PR_PINS Offset_global_assignment -name PR_PINS_OPEN_DRAIN Offset_global_assignment -name CLAMPING_DIODE Offset_global_assignment -name TRI_STATE_SPI_PINS Offset_global_assignment -name UNUSED_TSD_PINS_GND Offset_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Offset_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Offset_global_assignment -name ALM_REGISTER_PACKING_EFFORT MEDIUMset_global_assignment -name EDA_SIMULATION_TOOL "<None>"set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION Onset_global_assignment -name COMPRESSION_MODE Offset_global_assignment -name CLOCK_SOURCE Internalset_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Onset_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Offset_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Onset_global_assignment -name MAX7000S_JTAG_USER_CODE FFFFset_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFFset_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFFset_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFFset_global_assignment -name FLEX10K_JTAG_USER_CODE 7Fset_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFFset_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Offset_global_assignment -name USE_CHECKSUM_AS_USERCODE Onset_global_assignment -name SECURITY_BIT Offset_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III"set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III LS"set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix III"set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Autoset_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Autoset_global_assignment -name APEX20K_CONFIGURATION_DEVICE Autoset_global_assignment -name MERCURY_CONFIGURATION_DEVICE Autoset_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Autoset_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Autoset_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Autoset_global_assignment -name STRATIX_CONFIGURATION_DEVICE Autoset_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFFset_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFFset_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFFset_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFFset_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Offset_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE Onset_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Offset_global_assignment -name GENERATE_TTF_FILE Offset_global_assignment -name GENERATE_RBF_FILE Offset_global_assignment -name GENERATE_HEX_FILE Offset_global_assignment -name HEXOUT_FILE_START_ADDRESS 0set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Upset_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Offset_global_assignment -name AUTO_RESTART_CONFIGURATION Onset_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Offset_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Offset_global_assignment -name CYCLONEII_M4K_COMPATIBILITY Onset_global_assignment -name ENABLE_OCT_DONE Offset_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFFset_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Offset_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Offset_global_assignment -name START_TIME 0nsset_global_assignment -name SIMULATION_MODE TIMINGset_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Offset_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS Onset_global_assignment -name SETUP_HOLD_DETECTION Offset_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Offset_global_assignment -name CHECK_OUTPUTS Offset_global_assignment -name SIMULATION_COVERAGE Onset_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL Onset_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL Onset_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL Onset_global_assignment -name GLITCH_DETECTION Offset_global_assignment -name GLITCH_INTERVAL 1nsset_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Offset_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF Onset_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Offset_global_assignment -name SIMULATION_VDB_RESULT_FLUSH Onset_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGEset_global_assignment -name SIMULATION_NETLIST_VIEWER Offset_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORTset_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORTset_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Offset_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTOset_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTOset_global_assignment -name DRC_TOP_FANOUT 50set_global_assignment -name DRC_FANOUT_EXCEEDING 30set_global_assignment -name DRC_GATED_CLOCK_FEED 30set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLYset_global_assignment -name ENABLE_DRC_SETTINGS Offset_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2set_global_assignment -name MERGE_HEX_FILE Offset_global_assignment -name GENERATE_SVF_FILE Offset_global_assignment -name GENERATE_ISC_FILE Offset_global_assignment -name GENERATE_JAM_FILE Offset_global_assignment -name GENERATE_JBC_FILE Offset_global_assignment -name GENERATE_JBC_FILE_COMPRESSED Onset_global_assignment -name GENERATE_CONFIG_SVF_FILE Offset_global_assignment -name GENERATE_CONFIG_ISC_FILE Offset_global_assignment -name GENERATE_CONFIG_JAM_FILE Offset_global_assignment -name GENERATE_CONFIG_JBC_FILE Offset_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED Onset_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Offset_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Offset_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Offset_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%set_global_assignment -name POWER_USE_PVA Onset_global_assignment -name POWER_USE_INPUT_FILE "No File"set_global_assignment -name POWER_USE_INPUT_FILES Offset_global_assignment -name POWER_VCD_FILTER_GLITCHES Onset_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Offset_global_assignment -name POWER_REPORT_POWER_DISSIPATION Offset_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICALset_global_assignment -name POWER_AUTO_COMPUTE_TJ Onset_global_assignment -name POWER_TJ_VALUE 25set_global_assignment -name POWER_USE_TA_VALUE 25set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Offset_global_assignment -name POWER_BOARD_TEMPERATURE 25set_global_assignment -name POWER_HPS_ENABLE Offset_global_assignment -name POWER_HPS_PROC_FREQ 0.0set_global_assignment -name IGNORE_PARTITIONS Offset_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Offset_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING Onset_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS Onset_global_assignment -name RTLV_SIMPLIFIED_LOGIC Onset_global_assignment -name RTLV_GROUP_RELATED_NODES Onset_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Offset_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Offset_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV Onset_global_assignment -name EQC_CONSTANT_DFF_DETECTION Onset_global_assignment -name EQC_DUPLICATE_DFF_DETECTION Onset_global_assignment -name EQC_BBOX_MERGE Onset_global_assignment -name EQC_LVDS_MERGE Onset_global_assignment -name EQC_RAM_UNMERGING Onset_global_assignment -name EQC_DFF_SS_EMULATION Onset_global_assignment -name EQC_RAM_REGISTER_UNPACK Onset_global_assignment -name EQC_MAC_REGISTER_UNPACK Onset_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND Onset_global_assignment -name EQC_STRUCTURE_MATCHING Onset_global_assignment -name EQC_AUTO_BREAK_CONE Onset_global_assignment -name EQC_POWER_UP_COMPARE Offset_global_assignment -name EQC_AUTO_COMP_LOOP_CUT Onset_global_assignment -name EQC_AUTO_INVERSION Onset_global_assignment -name EQC_AUTO_TERMINATE Onset_global_assignment -name EQC_SUB_CONE_REPORT Offset_global_assignment -name EQC_RENAMING_RULES Onset_global_assignment -name EQC_PARAMETER_CHECK Onset_global_assignment -name EQC_AUTO_PORTSWAP Onset_global_assignment -name EQC_DETECT_DONT_CARES Onset_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Offset_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p1 -section_id ?set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ?set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ?
Go to most recent revision | Compare with Previous | Blame | View Log