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<h1>ao68000 Module Reference</h1> </div>
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<!-- doxytag: class="ao68000" --><!-- doxytag: inherits="bus_control,registers,memory_registers,decoder,condition,alu,microcode_branch" -->
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<p><a href="classao68000-members.html">List of all members.</a></p>
<table class="memberdecls">
<tr><td colspan="2"><h2><a name="Inputs"></a>
Inputs</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classao68000.html#a6bee7e749a667293d6fbea8fc1380d12">CLK_I</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight"><p>WISHBONE Clock Input </p>
<a href="#a6bee7e749a667293d6fbea8fc1380d12"></a><br/></td></tr>
<br/>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classao68000.html#a5c903f753511ea2ec94145415549a148">reset_n</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight"><p>Asynchronous Reset Input </p>
<a href="#a5c903f753511ea2ec94145415549a148"></a><br/></td></tr>
<br/>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classao68000.html#abffdd6f5cefb3be32b6db5bfc6b56442">DAT_I</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight"><p>WISHBONE Master Data Input </p>
<a href="#abffdd6f5cefb3be32b6db5bfc6b56442"></a><br/></td></tr>
<br/>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classao68000.html#a818ab80622c2364eb33814a5ef1f33ba">ACK_I</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight"><p>WISHBONE Master Acknowledge Input:</p>
<ul>
<li>on normal cycle: acknowledge,</li>
<li>on interrupt acknowledge cycle: external vector provided on DAT_I[7:0]. </li>
</ul>
<a href="#a818ab80622c2364eb33814a5ef1f33ba"></a><br/></td></tr>
<br/>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classao68000.html#a2a1a525f5a12c4e4a67bdf9fdf6df2be">ERR_I</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight"><p>WISHBONE Master Error Input</p>
<ul>
<li>on normal cycle: bus error,</li>
<li>on interrupt acknowledge cycle: spurious interrupt. </li>
</ul>
<a href="#a2a1a525f5a12c4e4a67bdf9fdf6df2be"></a><br/></td></tr>
<br/>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classao68000.html#af26604192b486b62964b9fada0bc6aff">RTY_I</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight"><p>WISHBONE Master Retry Input</p>
<ul>
<li>on normal cycle: retry bus cycle,</li>
<li>on interrupt acknowledge: use auto-vector. </li>
</ul>
<a href="#af26604192b486b62964b9fada0bc6aff"></a><br/></td></tr>
<br/>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classao68000.html#a1ff11e699c0192bb533209bd3cf9d5ba">ipl_i</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight"><p>Interrupt Priority Level Interrupt acknowledge cycle:</p>
<ul>
<li>ACK_I: interrupt vector on DAT_I[7:0],</li>
<li>ERR_I: spurious interrupt,</li>
<li>RTY_I: auto-vector. </li>
</ul>
<a href="#a1ff11e699c0192bb533209bd3cf9d5ba"></a><br/></td></tr>
<br/>
<tr><td colspan="2"><h2><a name="Outputs"></a>
Outputs</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classao68000.html#a61843aa9b51ba23ec6c8c35892366559">CYC_O</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight"><p>WISHBONE Master Cycle Output </p>
<a href="#a61843aa9b51ba23ec6c8c35892366559"></a><br/></td></tr>
<br/>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classao68000.html#a277895ba6004986cf490068945998fd0">ADR_O</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">2</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight"><p>WISHBONE Master Address Output </p>
<a href="#a277895ba6004986cf490068945998fd0"></a><br/></td></tr>
<br/>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classao68000.html#a801fbb1ae4c2812332242ce5d746cf36">DAT_O</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight"><p>WISHBONE Master Data Output </p>
<a href="#a801fbb1ae4c2812332242ce5d746cf36"></a><br/></td></tr>
<br/>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classao68000.html#ae636550dd8481fd101623d0c665e894c">SEL_O</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight"><p>WISHBONE Master Byte Select </p>
<a href="#ae636550dd8481fd101623d0c665e894c"></a><br/></td></tr>
<br/>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classao68000.html#a0e045730861ed97d585a192fcbbfd8a5">STB_O</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight"><p>WISHBONE Master Strobe Output </p>
<a href="#a0e045730861ed97d585a192fcbbfd8a5"></a><br/></td></tr>
<br/>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classao68000.html#a6cd0052d2c68597331280fe500366be4">WE_O</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight"><p>WISHBONE Master Write Enable Output </p>
<a href="#a6cd0052d2c68597331280fe500366be4"></a><br/></td></tr>
<br/>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classao68000.html#a067f51b370f090178fbe8248b48f50b0">SGL_O</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight"><p>WISHBONE Cycle Tag, TAG_TYPE: TGC_O, Single Bus Cycle. </p>
<a href="#a067f51b370f090178fbe8248b48f50b0"></a><br/></td></tr>
<br/>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classao68000.html#af57b8a8680a72f392a1f2af3ee2b61a9">BLK_O</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight"><p>WISHBONE Cycle Tag, TAG_TYPE: TGC_O, Block Bus Cycle. </p>
<a href="#af57b8a8680a72f392a1f2af3ee2b61a9"></a><br/></td></tr>
<br/>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classao68000.html#a951678555b50fc9229fe9b553c7b09d0">RMW_O</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight"><p>WISHBONE Cycle Tag, TAG_TYPE: TGC_O, Read-Modify-Write Cycle. </p>
<a href="#a951678555b50fc9229fe9b553c7b09d0"></a><br/></td></tr>
<br/>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classao68000.html#a02037d382851d62248a83cbc35dd1529">CTI_O</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight"><p>WISHBONE Address Tag, TAG_TYPE: TGA_O, Cycle Type Identifier, Incrementing Bus Cycle or End-of-Burst Cycle. </p>
<a href="#a02037d382851d62248a83cbc35dd1529"></a><br/></td></tr>
<br/>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classao68000.html#a08f46078858b7e8b6f2dfe2f6ec20c84">BTE_O</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">1</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight"><p>WISHBONE Address Tag, TAG_TYPE: TGA_O, Burst Type Extension, always Linear Burst. </p>
<a href="#a08f46078858b7e8b6f2dfe2f6ec20c84"></a><br/></td></tr>
<br/>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classao68000.html#a4b66c96fdd706df792811882b6f9fa9b">fc_o</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight"><p>Custom TAG_TYPE: TGC_O, Cycle Tag, Processor Function Code:</p>
<ul>
<li>1 - user data,</li>
<li>2 - user program,</li>
<li>5 - supervisor data : all exception vector entries except reset,</li>
<li>6 - supervisor program : exception vector for reset,</li>
<li>7 - cpu space: interrupt acknowledge. </li>
</ul>
<a href="#a4b66c96fdd706df792811882b6f9fa9b"></a><br/></td></tr>
<br/>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classao68000.html#a8246303a982cd24ff7dcc7b36c3038e2">reset_o</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight"><p>External device reset. Output high when processing the RESET instruction. </p>
<a href="#a8246303a982cd24ff7dcc7b36c3038e2"></a><br/></td></tr>
<br/>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classao68000.html#a0a90a371e379531c8e466799ff5c3d49">blocked_o</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight"><p>Processor blocked indicator. The processor is blocked after a double bus error. </p>
<a href="#a0a90a371e379531c8e466799ff5c3d49"></a><br/></td></tr>
<br/>
<tr><td colspan="2"><h2><a name="Module Instances"></a>
Module Instances</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><a class="el" href="classao68000.html#a2c34e1b84d9fe30c49c5c814be3dc392">bus_control::bus_control_m</a> </b> </td><td class="memItemRight" valign="bottom"> <b>Module</b><em> <a class="el" href="classbus__control.html">bus_control</a></em></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><a class="el" href="classao68000.html#ad82deea9ab15d2e02890df123ad51fd9">registers::registers_m</a> </b> </td><td class="memItemRight" valign="bottom"> <b>Module</b><em> <a class="el" href="classregisters.html">registers</a></em></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><a class="el" href="classao68000.html#ab85a25c3b08b1de81856944a16fafd5d">memory_registers::memory_registers_m</a> </b> </td><td class="memItemRight" valign="bottom"> <b>Module</b><em> <a class="el" href="classmemory__registers.html">memory_registers</a></em></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><a class="el" href="classao68000.html#a6f5a57c27d91cf2c4092c71adf13ae81">decoder::decoder_m</a> </b> </td><td class="memItemRight" valign="bottom"> <b>Module</b><em> <a class="el" href="classdecoder.html">decoder</a></em></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><a class="el" href="classao68000.html#a30446f4f602b6185a7ed25e5aa8e470e">condition::condition_m</a> </b> </td><td class="memItemRight" valign="bottom"> <b>Module</b><em> <a class="el" href="classcondition.html">condition</a></em></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><a class="el" href="classao68000.html#a63ee30297781426b4dd11d052490997f">alu::alu_m</a> </b> </td><td class="memItemRight" valign="bottom"> <b>Module</b><em> <a class="el" href="classalu.html">alu</a></em></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><a class="el" href="classao68000.html#a753de474d4bdb41b494fed2539290cc4">microcode_branch::microcode_branch_m</a> </b> </td><td class="memItemRight" valign="bottom"> <b>Module</b><em> <a class="el" href="classmicrocode__branch.html">microcode_branch</a></em></td></tr>
<tr><td colspan="2"><h2><a name="Signals"></a>
Signals</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar">[</span><span class="vhdldigit">15</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classao68000.html#abef0ede1a300bfe80eeecc8d51a0afe0">sr</a> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar">[</span><span class="vhdldigit">1</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classao68000.html#a608eadff9f4d94d93a9a08c244e93aa7">size</a> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classao68000.html#aaf40157e76d59864abf62ffe1c4f605d">address</a> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classao68000.html#a4d00737f890e3080a8915e23668c2fe0">read_modify_write_flag</a> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classao68000.html#a341be6a91dd12d14293eaa53c7c254d2">data_read</a> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classao68000.html#ac7098386bafc8ad2194743a7ebbc3928">data_write</a> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classao68000.html#a5e28cd1d3701cc3d88dd0df22e697108">pc</a> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar">[</span><span class="vhdldigit">79</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classao68000.html#a3403e55545d6a49c4a4fa6f16cfe7126">prefetch_ir</a> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classao68000.html#af1ea9f43861e0bc71f86dbaa9b2d790a">operand1</a> </td></tr>
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<hr/><a name="_details"></a><h2>Detailed Description</h2>
<p><a class="el" href="classao68000.html" title="ao68000 top level module.">ao68000</a> top level module. </p>
<p>This module contains only instantiations of sub-modules and wire declarations. </p>
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00405">405</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
<hr/><h2>Member Data Documentation</h2>
<a class="anchor" id="a6bee7e749a667293d6fbea8fc1380d12"></a><!-- doxytag: member="ao68000::CLK_I" ref="a6bee7e749a667293d6fbea8fc1380d12" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a6bee7e749a667293d6fbea8fc1380d12">CLK_I</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p><p>WISHBONE Clock Input </p>
</p>
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00407">407</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a2a1a525f5a12c4e4a67bdf9fdf6df2be"></a><!-- doxytag: member="ao68000::ERR_I" ref="a2a1a525f5a12c4e4a67bdf9fdf6df2be" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a2a1a525f5a12c4e4a67bdf9fdf6df2be">ERR_I</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p><p>WISHBONE Master Error Input</p>
<ul>
<li>on normal cycle: bus error,</li>
<li>on interrupt acknowledge cycle: spurious interrupt. </li>
</ul>
</p>
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00419">419</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="af26604192b486b62964b9fada0bc6aff"></a><!-- doxytag: member="ao68000::RTY_I" ref="af26604192b486b62964b9fada0bc6aff" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#af26604192b486b62964b9fada0bc6aff">RTY_I</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p><p>WISHBONE Master Retry Input</p>
<ul>
<li>on normal cycle: retry bus cycle,</li>
<li>on interrupt acknowledge: use auto-vector. </li>
</ul>
</p>
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00420">420</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a067f51b370f090178fbe8248b48f50b0"></a><!-- doxytag: member="ao68000::SGL_O" ref="a067f51b370f090178fbe8248b48f50b0" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a067f51b370f090178fbe8248b48f50b0">SGL_O</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p><p>WISHBONE Cycle Tag, TAG_TYPE: TGC_O, Single Bus Cycle. </p>
</p>
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00423">423</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="af57b8a8680a72f392a1f2af3ee2b61a9"></a><!-- doxytag: member="ao68000::BLK_O" ref="af57b8a8680a72f392a1f2af3ee2b61a9" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#af57b8a8680a72f392a1f2af3ee2b61a9">BLK_O</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p><p>WISHBONE Cycle Tag, TAG_TYPE: TGC_O, Block Bus Cycle. </p>
</p>
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00424">424</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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</div>
<a class="anchor" id="a951678555b50fc9229fe9b553c7b09d0"></a><!-- doxytag: member="ao68000::RMW_O" ref="a951678555b50fc9229fe9b553c7b09d0" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a951678555b50fc9229fe9b553c7b09d0">RMW_O</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p><p>WISHBONE Cycle Tag, TAG_TYPE: TGC_O, Read-Modify-Write Cycle. </p>
</p>
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00425">425</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a02037d382851d62248a83cbc35dd1529"></a><!-- doxytag: member="ao68000::CTI_O" ref="a02037d382851d62248a83cbc35dd1529" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a02037d382851d62248a83cbc35dd1529">CTI_O</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p><p>WISHBONE Address Tag, TAG_TYPE: TGA_O, Cycle Type Identifier, Incrementing Bus Cycle or End-of-Burst Cycle. </p>
</p>
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00428">428</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a08f46078858b7e8b6f2dfe2f6ec20c84"></a><!-- doxytag: member="ao68000::BTE_O" ref="a08f46078858b7e8b6f2dfe2f6ec20c84" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a08f46078858b7e8b6f2dfe2f6ec20c84">BTE_O</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">1</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p><p>WISHBONE Address Tag, TAG_TYPE: TGA_O, Burst Type Extension, always Linear Burst. </p>
</p>
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00429">429</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a4b66c96fdd706df792811882b6f9fa9b"></a><!-- doxytag: member="ao68000::fc_o" ref="a4b66c96fdd706df792811882b6f9fa9b" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a4b66c96fdd706df792811882b6f9fa9b">fc_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p><p>Custom TAG_TYPE: TGC_O, Cycle Tag, Processor Function Code:</p>
<ul>
<li>1 - user data,</li>
<li>2 - user program,</li>
<li>5 - supervisor data : all exception vector entries except reset,</li>
<li>6 - supervisor program : exception vector for reset,</li>
<li>7 - cpu space: interrupt acknowledge. </li>
</ul>
</p>
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00432">432</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a1ff11e699c0192bb533209bd3cf9d5ba"></a><!-- doxytag: member="ao68000::ipl_i" ref="a1ff11e699c0192bb533209bd3cf9d5ba" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a1ff11e699c0192bb533209bd3cf9d5ba">ipl_i</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p><p>Interrupt Priority Level Interrupt acknowledge cycle:</p>
<ul>
<li>ACK_I: interrupt vector on DAT_I[7:0],</li>
<li>ERR_I: spurious interrupt,</li>
<li>RTY_I: auto-vector. </li>
</ul>
</p>
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00440">440</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a8246303a982cd24ff7dcc7b36c3038e2"></a><!-- doxytag: member="ao68000::reset_o" ref="a8246303a982cd24ff7dcc7b36c3038e2" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a8246303a982cd24ff7dcc7b36c3038e2">reset_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p><p>External device reset. Output high when processing the RESET instruction. </p>
</p>
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00441">441</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a5c903f753511ea2ec94145415549a148"></a><!-- doxytag: member="ao68000::reset_n" ref="a5c903f753511ea2ec94145415549a148" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a5c903f753511ea2ec94145415549a148">reset_n</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p><p>Asynchronous Reset Input </p>
</p>
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00408">408</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a0a90a371e379531c8e466799ff5c3d49"></a><!-- doxytag: member="ao68000::blocked_o" ref="a0a90a371e379531c8e466799ff5c3d49" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a0a90a371e379531c8e466799ff5c3d49">blocked_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p><p>Processor blocked indicator. The processor is blocked after a double bus error. </p>
</p>
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00442">442</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="abef0ede1a300bfe80eeecc8d51a0afe0"></a><!-- doxytag: member="ao68000::sr" ref="abef0ede1a300bfe80eeecc8d51a0afe0" args="wire[15:0]" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#abef0ede1a300bfe80eeecc8d51a0afe0">sr</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[15:0]]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00445">445</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a608eadff9f4d94d93a9a08c244e93aa7"></a><!-- doxytag: member="ao68000::size" ref="a608eadff9f4d94d93a9a08c244e93aa7" args="wire[1:0]" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a608eadff9f4d94d93a9a08c244e93aa7">size</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[1:0]]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00446">446</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="aaf40157e76d59864abf62ffe1c4f605d"></a><!-- doxytag: member="ao68000::address" ref="aaf40157e76d59864abf62ffe1c4f605d" args="wire[31:0]" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#aaf40157e76d59864abf62ffe1c4f605d">address</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[31:0]]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00447">447</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a3da831ef8ac6ec75b132d8d299115092"></a><!-- doxytag: member="ao68000::address_type" ref="a3da831ef8ac6ec75b132d8d299115092" args="wire" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a3da831ef8ac6ec75b132d8d299115092">address_type</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00448">448</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a4d00737f890e3080a8915e23668c2fe0"></a><!-- doxytag: member="ao68000::read_modify_write_flag" ref="a4d00737f890e3080a8915e23668c2fe0" args="wire" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a4d00737f890e3080a8915e23668c2fe0">read_modify_write_flag</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00449">449</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a341be6a91dd12d14293eaa53c7c254d2"></a><!-- doxytag: member="ao68000::data_read" ref="a341be6a91dd12d14293eaa53c7c254d2" args="wire[31:0]" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a341be6a91dd12d14293eaa53c7c254d2">data_read</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[31:0]]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00450">450</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="ac7098386bafc8ad2194743a7ebbc3928"></a><!-- doxytag: member="ao68000::data_write" ref="ac7098386bafc8ad2194743a7ebbc3928" args="wire[31:0]" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#ac7098386bafc8ad2194743a7ebbc3928">data_write</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[31:0]]</code></td>
</tr>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00451">451</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a5e28cd1d3701cc3d88dd0df22e697108"></a><!-- doxytag: member="ao68000::pc" ref="a5e28cd1d3701cc3d88dd0df22e697108" args="wire[31:0]" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a5e28cd1d3701cc3d88dd0df22e697108">pc</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[31:0]]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00452">452</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a7f60c5a54b85d16a5daa159e3f93f3a2"></a><!-- doxytag: member="ao68000::prefetch_ir_valid" ref="a7f60c5a54b85d16a5daa159e3f93f3a2" args="wire" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a7f60c5a54b85d16a5daa159e3f93f3a2">prefetch_ir_valid</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire]</code></td>
</tr>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00453">453</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a61843aa9b51ba23ec6c8c35892366559"></a><!-- doxytag: member="ao68000::CYC_O" ref="a61843aa9b51ba23ec6c8c35892366559" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a61843aa9b51ba23ec6c8c35892366559">CYC_O</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p><p>WISHBONE Master Cycle Output </p>
</p>
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00410">410</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a3403e55545d6a49c4a4fa6f16cfe7126"></a><!-- doxytag: member="ao68000::prefetch_ir" ref="a3403e55545d6a49c4a4fa6f16cfe7126" args="wire[79:0]" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a3403e55545d6a49c4a4fa6f16cfe7126">prefetch_ir</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[79:0]]</code></td>
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</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00454">454</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a63cc96be1f84432ea4b755f14c9801bd"></a><!-- doxytag: member="ao68000::do_reset" ref="a63cc96be1f84432ea4b755f14c9801bd" args="wire" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a63cc96be1f84432ea4b755f14c9801bd">do_reset</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00455">455</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="aaa926f4340d9533fa404ed2121e01add"></a><!-- doxytag: member="ao68000::do_read" ref="aaa926f4340d9533fa404ed2121e01add" args="wire" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#aaa926f4340d9533fa404ed2121e01add">do_read</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00456">456</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a2fd644eba6903b45558dba81d759d60a"></a><!-- doxytag: member="ao68000::do_write" ref="a2fd644eba6903b45558dba81d759d60a" args="wire" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a2fd644eba6903b45558dba81d759d60a">do_write</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00457">457</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a017afb5ca18639747617179cd4b5b9af"></a><!-- doxytag: member="ao68000::do_interrupt" ref="a017afb5ca18639747617179cd4b5b9af" args="wire" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a017afb5ca18639747617179cd4b5b9af">do_interrupt</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00458">458</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a8d22354dba9690de7ed1f40174e7fac5"></a><!-- doxytag: member="ao68000::do_blocked" ref="a8d22354dba9690de7ed1f40174e7fac5" args="wire" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a8d22354dba9690de7ed1f40174e7fac5">do_blocked</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00459">459</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="aa9b27c579ff3359c8722f33ddc218606"></a><!-- doxytag: member="ao68000::jmp_address_trap" ref="aa9b27c579ff3359c8722f33ddc218606" args="wire" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#aa9b27c579ff3359c8722f33ddc218606">jmp_address_trap</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00460">460</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a68c0830ee44827649eeece60ccb007a4">jmp_bus_trap</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00461">461</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#adc838dee1d3e5fb81b69d9cd825e2078">finished</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00462">462</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#ab31d9d61b3fb7b8cf2d2588943144c51">interrupt_trap</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[7:0]]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00463">463</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a277895ba6004986cf490068945998fd0">ADR_O</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">2</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p><p>WISHBONE Master Address Output </p>
</p>
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00411">411</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00464">464</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#aa64aa2047c9823a2b6354f945b7a1e91">rw_state</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00465">465</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#ad29c33a9347a9dc0ad7e6a38a9674cea">fc_state</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[2:0]]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00466">466</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a2d3d54c5eadf71c6a422a5e9c3c1c0f0">decoder_trap</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[7:0]]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00467">467</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a0c5ac49d1bd4f956a99173ba8d76824e">usp</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[31:0]]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00468">468</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a9fbb4d38edd465bd6e91c844baa3cc32">Dn_output</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[31:0]]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00469">469</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a38819ff180e465048ac34fe24c17db2e">An_output</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[31:0]]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00470">470</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#ae78165f07b720df4d51db101effc08c5">result</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[31:0]]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00471">471</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#ac4bdc1d7a8df2e5b24f92e8c47b87d31">An_address</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[3:0]]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00472">472</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a314e14c9d14faca666d7282e70aec69e">An_input</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[31:0]]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00473">473</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a801fbb1ae4c2812332242ce5d746cf36"></a><!-- doxytag: member="ao68000::DAT_O" ref="a801fbb1ae4c2812332242ce5d746cf36" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a801fbb1ae4c2812332242ce5d746cf36">DAT_O</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p><p>WISHBONE Master Data Output </p>
</p>
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00412">412</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a8ce376b6468188948a66dd3090b82303">Dn_address</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[2:0]]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00474">474</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a88e0be4d7a8d7765fd81d2c7ecec034c">ir</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[15:0]]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00475">475</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a986f73747582af0c6343b171a856a806">decoder_micropc</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[8:0]]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00476">476</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00477">477</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#ab4eb4a01e79a4b7b88acd4f77c9acba4">load_ea</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[8:0]]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00478">478</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00479">479</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#aa0ab9326a484de5288f111934b0fd85d">perform_ea_write</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[8:0]]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00480">480</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00481">481</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#ad129761deda6ea56323f464ec70388cd">trace_flag</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00482">482</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a4421dfb45f06b1c0b54b098fdc26cb4e">group_0_flag</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00483">483</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#abffdd6f5cefb3be32b6db5bfc6b56442">DAT_I</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
</tr>
</table>
</div>
<div class="memdoc">
<p><p>WISHBONE Master Data Input </p>
</p>
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00413">413</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a8bb2b4e571e011cc39c0d1dd53f02145">stop_flag</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00484">484</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#af5e5eee4850873fc07b2bf4f35fa8ea0">micro_pc</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[8:0]]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00485">485</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="af1ea9f43861e0bc71f86dbaa9b2d790a"></a><!-- doxytag: member="ao68000::operand1" ref="af1ea9f43861e0bc71f86dbaa9b2d790a" args="wire[31:0]" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#af1ea9f43861e0bc71f86dbaa9b2d790a">operand1</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[31:0]]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00486">486</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a16f6886d59873ced06d573bf9f7df313">operand2</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[31:0]]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00487">487</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a9f1a061dfa48449c594659cc95fe794b"></a><!-- doxytag: member="ao68000::movem_loop" ref="a9f1a061dfa48449c594659cc95fe794b" args="wire[4:0]" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a9f1a061dfa48449c594659cc95fe794b">movem_loop</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[4:0]]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00488">488</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a23e8853dcd612e4f322f226cd105e979"></a><!-- doxytag: member="ao68000::movem_reg" ref="a23e8853dcd612e4f322f226cd105e979" args="wire[15:0]" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a23e8853dcd612e4f322f226cd105e979">movem_reg</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[15:0]]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00489">489</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
</div>
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<a class="anchor" id="a89c9e1f10192e0d67b9b1c905b9b9707"></a><!-- doxytag: member="ao68000::condition" ref="a89c9e1f10192e0d67b9b1c905b9b9707" args="wire" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a89c9e1f10192e0d67b9b1c905b9b9707">condition</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00490">490</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="ab3e5f1ab1be4d9610c68e34565365019"></a><!-- doxytag: member="ao68000::micro_data" ref="ab3e5f1ab1be4d9610c68e34565365019" args="wire[87:0]" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#ab3e5f1ab1be4d9610c68e34565365019">micro_data</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[87:0]]</code></td>
</tr>
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</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00491">491</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="ae5e0eb48c45313c4f859af77ec8cdac0"></a><!-- doxytag: member="ao68000::fault_address_state" ref="ae5e0eb48c45313c4f859af77ec8cdac0" args="wire[31:0]" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#ae5e0eb48c45313c4f859af77ec8cdac0">fault_address_state</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[31:0]]</code></td>
</tr>
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</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00492">492</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
</div>
</div>
<a class="anchor" id="ab2e4f443cf62f071af698fb3e623c57c"></a><!-- doxytag: member="ao68000::pc_change" ref="ab2e4f443cf62f071af698fb3e623c57c" args="wire[1:0]" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#ab2e4f443cf62f071af698fb3e623c57c">pc_change</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[1:0]]</code></td>
</tr>
</table>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00493">493</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
</div>
</div>
<a class="anchor" id="ae636550dd8481fd101623d0c665e894c"></a><!-- doxytag: member="ao68000::SEL_O" ref="ae636550dd8481fd101623d0c665e894c" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#ae636550dd8481fd101623d0c665e894c">SEL_O</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
</tr>
</table>
</div>
<div class="memdoc">
<p><p>WISHBONE Master Byte Select </p>
</p>
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00414">414</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a2386c661059b9a24d6a216ab668291e9"></a><!-- doxytag: member="ao68000::prefetch_ir_valid_32" ref="a2386c661059b9a24d6a216ab668291e9" args="wire" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a2386c661059b9a24d6a216ab668291e9">prefetch_ir_valid_32</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire]</code></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00494">494</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="ac7a12b8825569a6208688d0de8b91eb4"></a><!-- doxytag: member="ao68000::ea_type" ref="ac7a12b8825569a6208688d0de8b91eb4" args="wire[3:0]" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#ac7a12b8825569a6208688d0de8b91eb4">ea_type</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[3:0]]</code></td>
</tr>
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</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00495">495</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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</div>
<a class="anchor" id="a37c05e240e16bd7e15f95147f933f4e7"></a><!-- doxytag: member="ao68000::ea_mod" ref="a37c05e240e16bd7e15f95147f933f4e7" args="wire[2:0]" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a37c05e240e16bd7e15f95147f933f4e7">ea_mod</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[2:0]]</code></td>
</tr>
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</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00496">496</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a030de97afa9980f4d76f7c6e64419dc2"></a><!-- doxytag: member="ao68000::ea_reg" ref="a030de97afa9980f4d76f7c6e64419dc2" args="wire[2:0]" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a030de97afa9980f4d76f7c6e64419dc2">ea_reg</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[2:0]]</code></td>
</tr>
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</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00497">497</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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</div>
<a class="anchor" id="a0e045730861ed97d585a192fcbbfd8a5"></a><!-- doxytag: member="ao68000::STB_O" ref="a0e045730861ed97d585a192fcbbfd8a5" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a0e045730861ed97d585a192fcbbfd8a5">STB_O</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
</tr>
</table>
</div>
<div class="memdoc">
<p><p>WISHBONE Master Strobe Output </p>
</p>
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00415">415</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a6cd0052d2c68597331280fe500366be4">WE_O</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
</tr>
</table>
</div>
<div class="memdoc">
<p><p>WISHBONE Master Write Enable Output </p>
</p>
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00416">416</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a818ab80622c2364eb33814a5ef1f33ba"></a><!-- doxytag: member="ao68000::ACK_I" ref="a818ab80622c2364eb33814a5ef1f33ba" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a818ab80622c2364eb33814a5ef1f33ba">ACK_I</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
</tr>
</table>
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<div class="memdoc">
<p><p>WISHBONE Master Acknowledge Input:</p>
<ul>
<li>on normal cycle: acknowledge,</li>
<li>on interrupt acknowledge cycle: external vector provided on DAT_I[7:0]. </li>
</ul>
</p>
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00418">418</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a63ee30297781426b4dd11d052490997f">alu</a></span> <b><span class="vhdlchar">alu_m</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Module Instance]</code></td>
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</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00673">673</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a2c34e1b84d9fe30c49c5c814be3dc392">bus_control</a></span> <b><span class="vhdlchar">bus_control_m</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Module Instance]</code></td>
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</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00499">499</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a30446f4f602b6185a7ed25e5aa8e470e"></a><!-- doxytag: member="ao68000::condition" ref="a30446f4f602b6185a7ed25e5aa8e470e" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a30446f4f602b6185a7ed25e5aa8e470e">condition</a></span> <b><span class="vhdlchar">condition_m</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Module Instance]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00667">667</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a6f5a57c27d91cf2c4092c71adf13ae81">decoder</a></span> <b><span class="vhdlchar">decoder_m</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Module Instance]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00649">649</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="ab85a25c3b08b1de81856944a16fafd5d"></a><!-- doxytag: member="ao68000::memory_registers" ref="ab85a25c3b08b1de81856944a16fafd5d" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#ab85a25c3b08b1de81856944a16fafd5d">memory_registers</a></span> <b><span class="vhdlchar">memory_registers_m</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Module Instance]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00632">632</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a753de474d4bdb41b494fed2539290cc4"></a><!-- doxytag: member="ao68000::microcode_branch" ref="a753de474d4bdb41b494fed2539290cc4" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#a753de474d4bdb41b494fed2539290cc4">microcode_branch</a></span> <b><span class="vhdlchar">microcode_branch_m</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Module Instance]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00688">688</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="ad82deea9ab15d2e02890df123ad51fd9"></a><!-- doxytag: member="ao68000::registers" ref="ad82deea9ab15d2e02890df123ad51fd9" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classao68000.html#ad82deea9ab15d2e02890df123ad51fd9">registers</a></span> <b><span class="vhdlchar">registers_m</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Module Instance]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00551">551</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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