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<a href="#Inputs">Inputs</a> &#124;
<a href="#Outputs">Outputs</a> &#124;
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<a href="#Module Instances">Module Instances</a> &#124;
<a href="#Always Constructs">Always Constructs</a>  </div>
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<h1>memory_registers Module Reference</h1>  </div>
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<!-- doxytag: class="memory_registers" -->
<p>Contains the microcode ROM and D0-D7, A0-A7 registers.  
<a href="#_details">More...</a></p>
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Inheritance diagram for memory_registers:<!-- endSectionHeader --></div>
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<p><a href="classmemory__registers-members.html">List of all members.</a></p>
<table class="memberdecls">
<tr><td colspan="2"><h2><a name="Always Constructs"></a>
Always Constructs</h2></td></tr>
 <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a833db0d5eda614d712b846b259c0f4d3">ALWAYS_30</a>&#160;</td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classmemory__registers.html#a4d664c63ba14fa2b1664eb44203191fa">clock</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classmemory__registers.html#a431adf2f23f5aaf563824a502920385e">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
<tr><td colspan="2"><h2><a name="Inputs"></a>
Inputs</h2></td></tr>
 <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a4d664c63ba14fa2b1664eb44203191fa">clock</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a431adf2f23f5aaf563824a502920385e">reset_n</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a8d14d4f6f8c5706382c7f69b9e372660">An_address</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#ada61c344785639f1dff0853342ffc0e2">An_input</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a388c5aa2ed803d7f8fe0de1afc4ce0b3">An_write_enable</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a452091de9055b5a8c4b3a24f832bbff4">Dn_address</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a648512e0b41016edfe8de5136ddd1c06">Dn_input</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#afca18b6c4dc049b6c423a8bec09d6d76">Dn_write_enable</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a71a1a19e94fca451263e5f59daf32bbc">Dn_size</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a9d473ab60fc9c54280c725306fd4a60e">micro_pc</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">8</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
<tr><td colspan="2"><h2><a name="Outputs"></a>
Outputs</h2></td></tr>
 <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#ad83e80e6d6181078383f523cd155b88d">An_output</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#aa2114065af0aee3f968f55ab8d0cdd32">usp</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a992b24ce3987b39fc0bd77a602b8501c">Dn_output</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a6b80d6fab3ba246fa01c780bd1754229">micro_data</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">87</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
<tr><td colspan="2"><h2><a name="Module Instances"></a>
Module Instances</h2></td></tr>
 <tr><td class="memItemLeft" align="right" valign="top"><b><a class="el" href="classmemory__registers.html#a892186b1bfe856b1ddaf1d8b3a448f50">altsyncram::an_ram_inst</a>  </b>&#160;</td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><a class="el" href="classmemory__registers.html#a5b0f1fb5a259a06899ac6ac3b52835e0">altsyncram::dn_ram_inst</a>  </b>&#160;</td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><a class="el" href="classmemory__registers.html#afc54073a43b749eb1f1376c4b31cd1e3">altsyncram::micro_rom_inst</a>  </b>&#160;</td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td colspan="2"><h2><a name="Signals"></a>
Signals</h2></td></tr>
 <tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar"> </span></b> &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="classmemory__registers.html#a6b262496d8e72511014d422843dc16cb">An_ram_write_enable</a> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="classmemory__registers.html#a3d04ddf3e78cabbf0585da3688abb8b1">An_ram_output</a> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="classmemory__registers.html#af880499b12dc0f4afad0fdf7500bc3bf">dn_byteena</a> </td></tr>
</table>
<hr/><a name="_details"></a><h2>Detailed Description</h2>
<p>Contains the microcode ROM and D0-D7, A0-A7 registers. </p>
<p>The <a class="el" href="classmemory__registers.html" title="Contains the microcode ROM and D0-D7, A0-A7 registers.">memory_registers</a> module contains:</p>
<ul>
<li>data and address registers (D0-D7, A0-A7) implemented as an on-chip RAM.</li>
<li>the microcode implemented as an on-chip ROM.</li>
</ul>
<p>Currently this module contains <em>altsyncram</em> instantiations from Altera Megafunction/LPM library. </p>
 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02059">2059</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
<hr/><h2>Member Function Documentation</h2>
<a class="anchor" id="a833db0d5eda614d712b846b259c0f4d3"></a><!-- doxytag: member="memory_registers::ALWAYS_30" ref="a833db0d5eda614d712b846b259c0f4d3" args="clock, reset_n" -->
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          <td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_30          <td></td>
          <td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classmemory__registers.html#a4d664c63ba14fa2b1664eb44203191fa">clock</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> , </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classmemory__registers.html#a431adf2f23f5aaf563824a502920385e">reset_n</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> ) </td>
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<code> [Always Construct]</code></td>
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</div>
<div class="memdoc">
 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02092">2092</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
<div class="fragment"><pre class="fragment"> 
<a name="l02092"></a>02092 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classmemory__registers.html#a4d664c63ba14fa2b1664eb44203191fa">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classmemory__registers.html#a431adf2f23f5aaf563824a502920385e">reset_n</a>) <span class="vhdlkeyword">begin</span>
<a name="l02093"></a>02093     <span class="vhdlkeyword">if</span>(<a class="code" href="classmemory__registers.html#a431adf2f23f5aaf563824a502920385e">reset_n</a> == <span class="vhdllogic">1&#39;b0</span>)                                 <a class="code" href="classmemory__registers.html#aa2114065af0aee3f968f55ab8d0cdd32">usp</a> &lt;= <span class="vhdllogic">32&#39;d0</span>;
<a name="l02094"></a>02094     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classmemory__registers.html#a8d14d4f6f8c5706382c7f69b9e372660">An_address</a> == <span class="vhdllogic">4&#39;b0111</span> &amp;&amp; <a class="code" href="classmemory__registers.html#a388c5aa2ed803d7f8fe0de1afc4ce0b3">An_write_enable</a>)   <a class="code" href="classmemory__registers.html#aa2114065af0aee3f968f55ab8d0cdd32">usp</a> &lt;= <a class="code" href="classmemory__registers.html#ada61c344785639f1dff0853342ffc0e2">An_input</a>;
<a name="l02095"></a>02095 <span class="vhdlkeyword">end</span>
</pre></div>
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</div>
<hr/><h2>Member Data Documentation</h2>
<a class="anchor" id="a4d664c63ba14fa2b1664eb44203191fa"></a><!-- doxytag: member="memory_registers::clock" ref="a4d664c63ba14fa2b1664eb44203191fa" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a4d664c63ba14fa2b1664eb44203191fa">clock</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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</div>
<div class="memdoc">
 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02060">2060</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
 
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<a class="anchor" id="a431adf2f23f5aaf563824a502920385e"></a><!-- doxytag: member="memory_registers::reset_n" ref="a431adf2f23f5aaf563824a502920385e" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a431adf2f23f5aaf563824a502920385e">reset_n</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02061">2061</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
 
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<a class="anchor" id="a8d14d4f6f8c5706382c7f69b9e372660"></a><!-- doxytag: member="memory_registers::An_address" ref="a8d14d4f6f8c5706382c7f69b9e372660" args="" -->
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        <tr>
          <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a8d14d4f6f8c5706382c7f69b9e372660">An_address</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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      </table>
</div>
<div class="memdoc">
 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02064">2064</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
 
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<a class="anchor" id="ada61c344785639f1dff0853342ffc0e2"></a><!-- doxytag: member="memory_registers::An_input" ref="ada61c344785639f1dff0853342ffc0e2" args="" -->
<div class="memitem">
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      <table class="memname">
        <tr>
          <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#ada61c344785639f1dff0853342ffc0e2">An_input</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02065">2065</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
 
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<a class="anchor" id="a388c5aa2ed803d7f8fe0de1afc4ce0b3"></a><!-- doxytag: member="memory_registers::An_write_enable" ref="a388c5aa2ed803d7f8fe0de1afc4ce0b3" args="" -->
<div class="memitem">
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      <table class="memname">
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          <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a388c5aa2ed803d7f8fe0de1afc4ce0b3">An_write_enable</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02066">2066</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
 
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<a class="anchor" id="ad83e80e6d6181078383f523cd155b88d"></a><!-- doxytag: member="memory_registers::An_output" ref="ad83e80e6d6181078383f523cd155b88d" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#ad83e80e6d6181078383f523cd155b88d">An_output</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02067">2067</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
 
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<a class="anchor" id="aa2114065af0aee3f968f55ab8d0cdd32"></a><!-- doxytag: member="memory_registers::usp" ref="aa2114065af0aee3f968f55ab8d0cdd32" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#aa2114065af0aee3f968f55ab8d0cdd32">usp</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02069">2069</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
 
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<a class="anchor" id="a452091de9055b5a8c4b3a24f832bbff4"></a><!-- doxytag: member="memory_registers::Dn_address" ref="a452091de9055b5a8c4b3a24f832bbff4" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a452091de9055b5a8c4b3a24f832bbff4">Dn_address</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02071">2071</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
 
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<a class="anchor" id="a648512e0b41016edfe8de5136ddd1c06"></a><!-- doxytag: member="memory_registers::Dn_input" ref="a648512e0b41016edfe8de5136ddd1c06" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a648512e0b41016edfe8de5136ddd1c06">Dn_input</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02072">2072</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
 
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<a class="anchor" id="afca18b6c4dc049b6c423a8bec09d6d76"></a><!-- doxytag: member="memory_registers::Dn_write_enable" ref="afca18b6c4dc049b6c423a8bec09d6d76" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#afca18b6c4dc049b6c423a8bec09d6d76">Dn_write_enable</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02073">2073</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
 
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<a class="anchor" id="a71a1a19e94fca451263e5f59daf32bbc"></a><!-- doxytag: member="memory_registers::Dn_size" ref="a71a1a19e94fca451263e5f59daf32bbc" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a71a1a19e94fca451263e5f59daf32bbc">Dn_size</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02075">2075</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
 
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<a class="anchor" id="a992b24ce3987b39fc0bd77a602b8501c"></a><!-- doxytag: member="memory_registers::Dn_output" ref="a992b24ce3987b39fc0bd77a602b8501c" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a992b24ce3987b39fc0bd77a602b8501c">Dn_output</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02076">2076</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
 
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<a class="anchor" id="a9d473ab60fc9c54280c725306fd4a60e"></a><!-- doxytag: member="memory_registers::micro_pc" ref="a9d473ab60fc9c54280c725306fd4a60e" args="" -->
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02078">2078</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
 
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<a class="anchor" id="a6b80d6fab3ba246fa01c780bd1754229"></a><!-- doxytag: member="memory_registers::micro_data" ref="a6b80d6fab3ba246fa01c780bd1754229" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a6b80d6fab3ba246fa01c780bd1754229">micro_data</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">87</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02079">2079</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
 
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          <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a6b262496d8e72511014d422843dc16cb">An_ram_write_enable</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02082">2082</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
 
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02084">2084</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
 
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<a class="anchor" id="af880499b12dc0f4afad0fdf7500bc3bf"></a><!-- doxytag: member="memory_registers::dn_byteena" ref="af880499b12dc0f4afad0fdf7500bc3bf" args="wire[3:0]" -->
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02087">2087</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
 
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<a class="anchor" id="afc54073a43b749eb1f1376c4b31cd1e3"></a><!-- doxytag: member="memory_registers::altsyncram" ref="afc54073a43b749eb1f1376c4b31cd1e3" args="" -->
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02130">2130</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
 
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<a class="anchor" id="a5b0f1fb5a259a06899ac6ac3b52835e0"></a><!-- doxytag: member="memory_registers::altsyncram" ref="a5b0f1fb5a259a06899ac6ac3b52835e0" args="" -->
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02114">2114</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
 
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<a class="anchor" id="a892186b1bfe856b1ddaf1d8b3a448f50"></a><!-- doxytag: member="memory_registers::altsyncram" ref="a892186b1bfe856b1ddaf1d8b3a448f50" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a892186b1bfe856b1ddaf1d8b3a448f50">altsyncram</a></span> <b><span class="vhdlchar">an_ram_inst</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Module Instance]</code></td>
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02098">2098</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
 
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<hr/>The documentation for this class was generated from the following file:<ul>
<li><a class="el" href="ao68000_8v_source.html">ao68000.v</a></li>
</ul>
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<hr class="footer"/><address class="footer"><small>Generated on Sat Jan 15 2011 22:20:15 for ao68000 by&#160;
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.2 </small></address>
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