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<h1>registers Module Reference</h1> </div>
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<p>Microcode controlled registers.
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Inheritance diagram for registers:<!-- endSectionHeader --></div>
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<tr><td colspan="2"><h2><a name="Always Constructs"></a>
Always Constructs</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#a1634ef9b02cbeb72da694a9145e2d276">ALWAYS_2</a> </td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#a160e4dadb225ac705317bf8de0c78277">ALWAYS_3</a> </td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#a098bb8c5f886c173a49d1e015dd37289">ALWAYS_4</a> </td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#a6fc98500064486297076cc7c8e99e16f">ALWAYS_5</a> </td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#aa536be1ed88148e7c828c0183e8a0757">ALWAYS_6</a> </td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#a8fa9503b229756474eafc4b087aa6511">ALWAYS_7</a> </td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#ae6143c84411ad159cbe1662f3909e726">ALWAYS_8</a> </td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#ae04888e60d745f9f64ca5c52d0969adb">ALWAYS_9</a> </td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#a7943ebd2393533b177f2cc9471614403">ALWAYS_10</a> </td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#a57a4884a23011ba445e6a69044c0b0bc">ALWAYS_11</a> </td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#a84ce568fcbe169cc02a3dc5c5bdbced2">ALWAYS_12</a> </td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#a5ca9e5ee3853a6c58d80397ee08dcdfb">ALWAYS_13</a> </td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#a670e4db98926f8ddddaa84356173ff1a">ALWAYS_14</a> </td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#a3a2e5a5ea0bbf7d06bee2afef1124393">ALWAYS_15</a> </td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#a931eb6b9c3c3c002a0eea00a7f10e10f">ALWAYS_16</a> </td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#a2a04a4a12e64f1ffb3ec95095716fee7">ALWAYS_17</a> </td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#af284685eb0240e8fc444c84618b1af67">ALWAYS_18</a> </td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#a12d4c2e0121456bcb2b23e7444c1da06">ALWAYS_19</a> </td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#acf180186b03cdc0ad93be0efb7fa2815">ALWAYS_20</a> </td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#a328ee93f9ab0ed3ebab4dc5936a7c5a0">ALWAYS_21</a> </td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#ad172a9061d9bb3653a3996dc4a74e101">ALWAYS_22</a> </td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#a34326a20d0a44ce95c7da4da53005097">ALWAYS_23</a> </td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#ad881b4aebf8b3df42129f9731b6f6098">ALWAYS_24</a> </td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#aa69b93f001339d4b8ae1295a5cb215ec">ALWAYS_25</a> </td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#a63d22bb9298a179653d09d6b21e6c68b">ALWAYS_26</a> </td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#a66ffba6d56dd08fe7b968605c3b68465">ALWAYS_27</a> </td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#ab3c53c1dc1763e2d051eaa736e429d58">ALWAYS_28</a> </td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
<tr><td colspan="2"><h2><a name="Inputs"></a>
Inputs</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#a015db9817045d85028931bbb036f7b59">data_read</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">79</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#aabb30e872d04701c156a70c4e1e7a3ba">prefetch_ir_valid</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#a81ed0f1a7f814e74696bea4db63f1e31">result</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#ad583f99f893a13448ecd261e637ad56b">sr</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">15</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#a881b6927205941e0691b73906a7cfdd9">rw_state</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#af336bd0ea96aad806fdb36dcd673a9c2">fc_state</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#a2975efdebb48903a858f0558c58d31c2">fault_address_state</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#ad7009ed104b0324325f2ebe297edc9b4">interrupt_trap</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">7</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#aaa89ede670fdc60f2b18c637c50f0dff">interrupt_mask</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#a1444e3b474fdf49e5ab8a0283060ceab">decoder_trap</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">7</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#ae8312cd504b37ae6dc199537ddf93bcb">usp</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#a0376be737f05fcad48a8057caa2f1fcf">Dn_output</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#a4076832588fccdd9d5d0cc1b4b8dd0b0">An_output</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#a87fed6b8d7f55252c49ab2fc43d39d9a">ea_reg_control</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#a6fe315cf4e9805733719db71cf630847">ea_type_control</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td colspan="2"><h2><a name="Outputs"></a>
Outputs</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#a73560eea6b21f10073a1131e3cffa801">pc_change</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">1</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#a69652ae311e16ddcb1bb0dbc90744156">ea_reg</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#a531a4ea89d5bde45780adeeda7d42bb4">ea_type</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td colspan="2"><h2><a name="Signals"></a>
Signals</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classregisters.html#a87b4409ca50b4ccad122fad79a9d6665">pc_valid</a> </td></tr>
</table>
<hr/><a name="_details"></a><h2>Detailed Description</h2>
<p>Microcode controlled registers. </p>
<p>Most of the <a class="el" href="classao68000.html" title="ao68000 top level module.">ao68000</a> IP core registers are located in this module. At every clock cycle the microcode controls what to save into these registers. Some of the more important registers include:</p>
<ul>
<li>operand1, operand2 registers are inputs to the ALU,</li>
<li>address, size, do_read_flag, do_write_flag, do_interrupt_flag registers tell the <a class="el" href="classbus__control.html" title="Initiate WISHBONE MASTER bus cycles.">bus_control</a> module what kind of bus cycle to perform,</li>
<li>pc register stores the current program counter,</li>
<li>ir register stores the current instruction word,</li>
<li>ea_mod, ea_type registers store the currently selected addressing mode. </li>
</ul>
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01620">1620</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
<hr/><h2>Member Function Documentation</h2>
<a class="anchor" id="a7943ebd2393533b177f2cc9471614403"></a><!-- doxytag: member="registers::ALWAYS_10" ref="a7943ebd2393533b177f2cc9471614403" args="clock, reset_n" -->
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<div class="memproto">
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<td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_10 <td></td>
<td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> , </td>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> ) </td>
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<code> [Always Construct]</code></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01886">1886</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
<div class="fragment"><pre class="fragment">
<a name="l01886"></a>01886 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
<a name="l01887"></a>01887 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">address_type</span> <= <span class="vhdllogic">1'b0</span>;
<a name="l01888"></a>01888 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#aa7a6ef5c21bbbf8a3c5a0437bdda3c85">`ADDRESS_FROM_PC_INDEX_OFFSET</a><span class="vhdlchar"></span>) <span class="vhdlchar">address_type</span> <= <span class="vhdllogic">1'b1</span>;
<a name="l01889"></a>01889 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> != <a class="code" href="ao68000_8v.html#a3f7506465d358bddd4692916e422237d">`ADDRESS_IDLE</a><span class="vhdlchar"></span>) <span class="vhdlchar">address_type</span> <= <span class="vhdllogic">1'b0</span>;
<a name="l01890"></a>01890 <span class="vhdlkeyword">end</span>
</pre></div>
</div>
</div>
<a class="anchor" id="a57a4884a23011ba445e6a69044c0b0bc"></a><!-- doxytag: member="registers::ALWAYS_11" ref="a57a4884a23011ba445e6a69044c0b0bc" args="clock, reset_n" -->
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<td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_11 <td></td>
<td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> , </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> ) </td>
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<code> [Always Construct]</code></td>
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</table>
</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01892">1892</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
<div class="fragment"><pre class="fragment">
<a name="l01892"></a>01892 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
<a name="l01893"></a>01893 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">movem_modreg</span> <= <span class="vhdllogic">6'b0</span>;
<a name="l01894"></a>01894 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">movem_modreg_control</span> == <a class="code" href="ao68000_8v.html#a59e6a074af6fbcf3490ecdb2d277e452">`MOVEM_MODREG_LOAD_0</a><span class="vhdlchar"></span>) <span class="vhdlchar">movem_modreg</span> <= <span class="vhdllogic">6'b0</span>;
<a name="l01895"></a>01895 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">movem_modreg_control</span> == <a class="code" href="ao68000_8v.html#a96857bc6f8514765cf6add0567891646">`MOVEM_MODREG_LOAD_6b001111</a><span class="vhdlchar"></span>)<span class="vhdlchar">movem_modreg</span> <= <span class="vhdllogic">6'b001111</span>;
<a name="l01896"></a>01896 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">movem_modreg_control</span> == <a class="code" href="ao68000_8v.html#ab865a06c214356bb8906149ad6beebf2">`MOVEM_MODREG_INCR_BY_1</a><span class="vhdlchar"></span>) <span class="vhdlchar">movem_modreg</span> <= <span class="vhdlchar">movem_modreg</span> + <span class="vhdllogic">6'd1</span>;
<a name="l01897"></a>01897 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">movem_modreg_control</span> == <a class="code" href="ao68000_8v.html#afc15f893a792d1af5e5c90f8ed788662">`MOVEM_MODREG_DECR_BY_1</a><span class="vhdlchar"></span>) <span class="vhdlchar">movem_modreg</span> <= <span class="vhdlchar">movem_modreg</span> - <span class="vhdllogic">6'd1</span>;
<a name="l01898"></a>01898 <span class="vhdlkeyword">end</span>
</pre></div>
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</div>
<a class="anchor" id="a84ce568fcbe169cc02a3dc5c5bdbced2"></a><!-- doxytag: member="registers::ALWAYS_12" ref="a84ce568fcbe169cc02a3dc5c5bdbced2" args="clock, reset_n" -->
<div class="memitem">
<div class="memproto">
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<td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_12 <td></td>
<td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> , </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> ) </td>
</tr>
<code> [Always Construct]</code></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01900">1900</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
<div class="fragment"><pre class="fragment">
<a name="l01900"></a>01900 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
<a name="l01901"></a>01901 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">movem_loop</span> <= <span class="vhdllogic">5'b0</span>;
<a name="l01902"></a>01902 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">movem_loop_control</span> == <a class="code" href="ao68000_8v.html#a8465e4a24e72c1cb6e12015c4ff806c5">`MOVEM_LOOP_LOAD_0</a><span class="vhdlchar"></span>) <span class="vhdlchar">movem_loop</span> <= <span class="vhdllogic">5'b0</span>;
<a name="l01903"></a>01903 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">movem_loop_control</span> == <a class="code" href="ao68000_8v.html#add999e8b65307d6d46547d776999f215">`MOVEM_LOOP_INCR_BY_1</a><span class="vhdlchar"></span>) <span class="vhdlchar">movem_loop</span> <= <span class="vhdlchar">movem_loop</span> + <span class="vhdllogic">5'd1</span>;
<a name="l01904"></a>01904 <span class="vhdlkeyword">end</span>
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<a class="anchor" id="a5ca9e5ee3853a6c58d80397ee08dcdfb"></a><!-- doxytag: member="registers::ALWAYS_13" ref="a5ca9e5ee3853a6c58d80397ee08dcdfb" args="clock, reset_n" -->
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<td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_13 <td></td>
<td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> , </td>
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<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> ) </td>
</tr>
<code> [Always Construct]</code></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01906">1906</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
<div class="fragment"><pre class="fragment">
<a name="l01906"></a>01906 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
<a name="l01907"></a>01907 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">movem_reg</span> <= <span class="vhdllogic">16'b0</span>;
<a name="l01908"></a>01908 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">movem_reg_control</span> == <a class="code" href="ao68000_8v.html#aa7d78c26e9e37f761c7a0b178fe13cf8">`MOVEM_REG_FROM_OP1</a><span class="vhdlchar"></span>) <span class="vhdlchar">movem_reg</span> <= <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>];
<a name="l01909"></a>01909 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">movem_reg_control</span> == <a class="code" href="ao68000_8v.html#ac34150d75e16d155befcfcb8a95e45a3">`MOVEM_REG_SHIFT_RIGHT</a><span class="vhdlchar"></span>) <span class="vhdlchar">movem_reg</span> <= { <span class="vhdllogic">1'b0</span>, <span class="vhdlchar">movem_reg</span>[<span class="vhdllogic">15</span>:<span class="vhdllogic">1</span>] };
<a name="l01910"></a>01910 <span class="vhdlkeyword">end</span>
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<a class="anchor" id="a670e4db98926f8ddddaa84356173ff1a"></a><!-- doxytag: member="registers::ALWAYS_14" ref="a670e4db98926f8ddddaa84356173ff1a" args="clock, reset_n" -->
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<td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_14 <td></td>
<td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> , </td>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> ) </td>
</tr>
<code> [Always Construct]</code></td>
</tr>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01912">1912</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
<div class="fragment"><pre class="fragment">
<a name="l01912"></a>01912 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
<a name="l01913"></a>01913 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">ir</span> <= <span class="vhdllogic">16'b0</span>;
<a name="l01914"></a>01914 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">ir_control</span> == <a class="code" href="ao68000_8v.html#a987216cfc97019736d0251dcd5470e68">`IR_LOAD_WHEN_PREFETCH_VALID</a><span class="vhdlchar"></span> && <a class="code" href="classregisters.html#aabb30e872d04701c156a70c4e1e7a3ba">prefetch_ir_valid</a> == <span class="vhdllogic">1'b1</span> && <span class="vhdlchar">stop_flag</span> == <span class="vhdllogic">1'b0</span>)
<a name="l01915"></a>01915 <span class="vhdlchar">ir</span> <= <a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">79</span>:<span class="vhdllogic">64</span>];
<a name="l01916"></a>01916 <span class="vhdlkeyword">end</span>
</pre></div>
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<a class="anchor" id="a3a2e5a5ea0bbf7d06bee2afef1124393"></a><!-- doxytag: member="registers::ALWAYS_15" ref="a3a2e5a5ea0bbf7d06bee2afef1124393" args="clock, reset_n" -->
<div class="memitem">
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<td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_15 <td></td>
<td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> , </td>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> ) </td>
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<code> [Always Construct]</code></td>
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</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01918">1918</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
<div class="fragment"><pre class="fragment">
<a name="l01918"></a>01918 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
<a name="l01919"></a>01919 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">trap</span> <= <span class="vhdllogic">8'd0</span>;
<a name="l01920"></a>01920 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trap_control</span> == <a class="code" href="ao68000_8v.html#a4267c71337dc6963db47aba754396f48">`TRAP_ILLEGAL_INSTR</a><span class="vhdlchar"></span>) <span class="vhdlchar">trap</span> <= <span class="vhdllogic">8'd4</span>;
<a name="l01921"></a>01921 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trap_control</span> == <a class="code" href="ao68000_8v.html#a111476f2c18a4085c9a5cea3692dc990">`TRAP_DIV_BY_ZERO</a><span class="vhdlchar"></span>) <span class="vhdlchar">trap</span> <= <span class="vhdllogic">8'd5</span>;
<a name="l01922"></a>01922 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trap_control</span> == <a class="code" href="ao68000_8v.html#a7d97a1e77166d92c1d69452c3e836682">`TRAP_CHK</a><span class="vhdlchar"></span>) <span class="vhdlchar">trap</span> <= <span class="vhdllogic">8'd6</span>;
<a name="l01923"></a>01923 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trap_control</span> == <a class="code" href="ao68000_8v.html#a66a7d33a63851daa49e101494acd6118">`TRAP_TRAPV</a><span class="vhdlchar"></span>) <span class="vhdlchar">trap</span> <= <span class="vhdllogic">8'd7</span>;
<a name="l01924"></a>01924 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trap_control</span> == <a class="code" href="ao68000_8v.html#a940b41a2a1e4c585e15f1c2bef5d5c6f">`TRAP_PRIVIL_VIOLAT</a><span class="vhdlchar"></span>) <span class="vhdlchar">trap</span> <= <span class="vhdllogic">8'd8</span>;
<a name="l01925"></a>01925 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trap_control</span> == <a class="code" href="ao68000_8v.html#a84705ced93a01047ec829b7ea942cee0">`TRAP_TRACE</a><span class="vhdlchar"></span>) <span class="vhdlchar">trap</span> <= <span class="vhdllogic">8'd9</span>;
<a name="l01926"></a>01926 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trap_control</span> == <a class="code" href="ao68000_8v.html#a4d09227bd9de91efc1a40bf676e10c72">`TRAP_TRAP</a><span class="vhdlchar"></span>) <span class="vhdlchar">trap</span> <= { <span class="vhdllogic">4'b0010</span>, <span class="vhdlchar">ir</span>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] };
<a name="l01927"></a>01927 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trap_control</span> == <a class="code" href="ao68000_8v.html#a8d6c015903e3a60339a6e8cc196bb440">`TRAP_FROM_DECODER</a><span class="vhdlchar"></span>) <span class="vhdlchar">trap</span> <= <a class="code" href="classregisters.html#a1444e3b474fdf49e5ab8a0283060ceab">decoder_trap</a>;
<a name="l01928"></a>01928 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trap_control</span> == <a class="code" href="ao68000_8v.html#a57812c3cf3905152a60361ae979a4c2d">`TRAP_FROM_INTERRUPT</a><span class="vhdlchar"></span>) <span class="vhdlchar">trap</span> <= <a class="code" href="classregisters.html#ad7009ed104b0324325f2ebe297edc9b4">interrupt_trap</a>;
<a name="l01929"></a>01929 <span class="vhdlkeyword">end</span>
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<a class="anchor" id="a931eb6b9c3c3c002a0eea00a7f10e10f"></a><!-- doxytag: member="registers::ALWAYS_16" ref="a931eb6b9c3c3c002a0eea00a7f10e10f" args="clock, reset_n" -->
<div class="memitem">
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<td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_16 <td></td>
<td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> , </td>
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<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> ) </td>
</tr>
<code> [Always Construct]</code></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01931">1931</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
<div class="fragment"><pre class="fragment">
<a name="l01931"></a>01931 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
<a name="l01932"></a>01932 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">offset</span> <= <span class="vhdllogic">32'd0</span>;
<a name="l01933"></a>01933 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">offset_control</span> == <a class="code" href="ao68000_8v.html#ad904ffb95a59f475e446877344adb415">`OFFSET_IMM_8</a><span class="vhdlchar"></span>) <span class="vhdlchar">offset</span> <= { {<span class="vhdllogic">24</span>{<a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">71</span>]}}, <a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">71</span>:<span class="vhdllogic">64</span>] };
<a name="l01934"></a>01934 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">offset_control</span> == <a class="code" href="ao68000_8v.html#a87c5da2d7633077683260709d88602e0">`OFFSET_IMM_16</a><span class="vhdlchar"></span>) <span class="vhdlchar">offset</span> <= { {<span class="vhdllogic">16</span>{<a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">79</span>]}}, <a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">79</span>:<span class="vhdllogic">64</span>] };
<a name="l01935"></a>01935 <span class="vhdlkeyword">end</span>
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<a class="anchor" id="a2a04a4a12e64f1ffb3ec95095716fee7"></a><!-- doxytag: member="registers::ALWAYS_17" ref="a2a04a4a12e64f1ffb3ec95095716fee7" args="clock, reset_n" -->
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<td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_17 <td></td>
<td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> , </td>
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<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> ) </td>
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<code> [Always Construct]</code></td>
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</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01937">1937</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
<div class="fragment"><pre class="fragment">
<a name="l01937"></a>01937 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
<a name="l01938"></a>01938 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">index</span> <= <span class="vhdllogic">32'd0</span>;
<a name="l01939"></a>01939 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">index_control</span> == <a class="code" href="ao68000_8v.html#a1db54bd70d82cea2a77c6d5c823f04db">`INDEX_0</a><span class="vhdlchar"></span>) <span class="vhdlchar">index</span> <= <span class="vhdllogic">32'd0</span>;
<a name="l01940"></a>01940 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">index_control</span> == <a class="code" href="ao68000_8v.html#af05405b84ee28262882d3c7ac7a5a80c">`INDEX_LOAD_EXTENDED</a><span class="vhdlchar"></span>) <span class="vhdlchar">index</span> <=
<a name="l01941"></a>01941 (<a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">79</span>] == <span class="vhdllogic">1'b0</span>) ?
<a name="l01942"></a>01942 ( (<a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">75</span>] == <span class="vhdllogic">1'b0</span>) ?
<a name="l01943"></a>01943 { {<span class="vhdllogic">16</span>{<a class="code" href="classregisters.html#a0376be737f05fcad48a8057caa2f1fcf">Dn_output</a>[<span class="vhdllogic">15</span>]}}, <a class="code" href="classregisters.html#a0376be737f05fcad48a8057caa2f1fcf">Dn_output</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] } : <a class="code" href="classregisters.html#a0376be737f05fcad48a8057caa2f1fcf">Dn_output</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>]
<a name="l01944"></a>01944 ) :
<a name="l01945"></a>01945 ( (<a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">75</span>] == <span class="vhdllogic">1'b0</span>) ?
<a name="l01946"></a>01946 { {<span class="vhdllogic">16</span>{<a class="code" href="classregisters.html#a4076832588fccdd9d5d0cc1b4b8dd0b0">An_output</a>[<span class="vhdllogic">15</span>]}}, <a class="code" href="classregisters.html#a4076832588fccdd9d5d0cc1b4b8dd0b0">An_output</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] } : <a class="code" href="classregisters.html#a4076832588fccdd9d5d0cc1b4b8dd0b0">An_output</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>]
<a name="l01947"></a>01947 );
<a name="l01948"></a>01948 <span class="vhdlkeyword">end</span>
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<a class="anchor" id="af284685eb0240e8fc444c84618b1af67"></a><!-- doxytag: member="registers::ALWAYS_18" ref="af284685eb0240e8fc444c84618b1af67" args="clock, reset_n" -->
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<td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_18 <td></td>
<td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> , </td>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> ) </td>
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<code> [Always Construct]</code></td>
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</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01950">1950</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
<div class="fragment"><pre class="fragment">
<a name="l01950"></a>01950 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
<a name="l01951"></a>01951 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">stop_flag</span> <= <span class="vhdllogic">1'b0</span>;
<a name="l01952"></a>01952 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">stop_flag_control</span> == <a class="code" href="ao68000_8v.html#a5131e7ee341cd6f2ea5350a89b19a488">`STOP_FLAG_SET</a><span class="vhdlchar"></span>) <span class="vhdlchar">stop_flag</span> <= <span class="vhdllogic">1'b1</span>;
<a name="l01953"></a>01953 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">stop_flag_control</span> == <a class="code" href="ao68000_8v.html#a0e63684fc863d639423c2d9f0f8e6cd9">`STOP_FLAG_CLEAR</a><span class="vhdlchar"></span>) <span class="vhdlchar">stop_flag</span> <= <span class="vhdllogic">1'b0</span>;
<a name="l01954"></a>01954 <span class="vhdlkeyword">end</span>
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<a class="anchor" id="a12d4c2e0121456bcb2b23e7444c1da06"></a><!-- doxytag: member="registers::ALWAYS_19" ref="a12d4c2e0121456bcb2b23e7444c1da06" args="clock, reset_n" -->
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<td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_19 <td></td>
<td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> , </td>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> ) </td>
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<code> [Always Construct]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01956">1956</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
<div class="fragment"><pre class="fragment">
<a name="l01956"></a>01956 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
<a name="l01957"></a>01957 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">trace_flag</span> <= <span class="vhdllogic">1'b0</span>;
<a name="l01958"></a>01958 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trace_flag_control</span> == <a class="code" href="ao68000_8v.html#a3cb5bcdd68537f527007213efe5c2d4f">`TRACE_FLAG_COPY_WHEN_NO_STOP</a><span class="vhdlchar"></span> && <a class="code" href="classregisters.html#aabb30e872d04701c156a70c4e1e7a3ba">prefetch_ir_valid</a> == <span class="vhdllogic">1'b1</span> && <a class="code" href="classregisters.html#a1444e3b474fdf49e5ab8a0283060ceab">decoder_trap</a> == <span class="vhdllogic">8'd0</span> && <span class="vhdlchar">stop_flag</span> == <span class="vhdllogic">1'b0</span>)
<a name="l01959"></a>01959 <span class="vhdlchar">trace_flag</span> <= <a class="code" href="classregisters.html#ad583f99f893a13448ecd261e637ad56b">sr</a>[<span class="vhdllogic">15</span>];
<a name="l01960"></a>01960 <span class="vhdlkeyword">end</span>
</pre></div>
</div>
</div>
<a class="anchor" id="a1634ef9b02cbeb72da694a9145e2d276"></a><!-- doxytag: member="registers::ALWAYS_2" ref="a1634ef9b02cbeb72da694a9145e2d276" args="clock, reset_n" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_2 <td></td>
<td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> , </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> ) </td>
</tr>
<code> [Always Construct]</code></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01737">1737</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
<div class="fragment"><pre class="fragment">
<a name="l01737"></a>01737 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
<a name="l01738"></a>01738 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
<a name="l01739"></a>01739 <span class="vhdlchar">pc</span> <= <span class="vhdllogic">32'd0</span>;
<a name="l01740"></a>01740 <a class="code" href="classregisters.html#a87b4409ca50b4ccad122fad79a9d6665">pc_valid</a> <= <span class="vhdllogic">32'd0</span>;
<a name="l01741"></a>01741 <span class="vhdlkeyword">end</span>
<a name="l01742"></a>01742 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
<a name="l01743"></a>01743 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">pc_control</span> == <a class="code" href="ao68000_8v.html#a63d3becb9e2a770cfd9df4a70298c30a">`PC_FROM_RESULT</a><span class="vhdlchar"></span>) <span class="vhdlchar">pc</span> = <a class="code" href="classregisters.html#a81ed0f1a7f814e74696bea4db63f1e31">result</a>;
<a name="l01744"></a>01744 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">pc_control</span> == <a class="code" href="ao68000_8v.html#a023942fcdb1eb88002847e9730cf62c2">`PC_INCR_BY_2</a><span class="vhdlchar"></span>) <span class="vhdlchar">pc</span> = <span class="vhdlchar">pc</span> + <span class="vhdllogic">32'd2</span>;
<a name="l01745"></a>01745 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">pc_control</span> == <a class="code" href="ao68000_8v.html#a6b8aff09ca5bd77e19e6d7a5076a58bd">`PC_INCR_BY_4</a><span class="vhdlchar"></span>) <span class="vhdlchar">pc</span> = <span class="vhdlchar">pc</span> + <span class="vhdllogic">32'd4</span>;
<a name="l01746"></a>01746 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">pc_control</span> == <a class="code" href="ao68000_8v.html#aefc526541d0911ae626689caead407ab">`PC_INCR_BY_SIZE</a><span class="vhdlchar"></span>) <span class="vhdlchar">pc</span> = (<span class="vhdlchar">size</span>[<span class="vhdllogic">2</span>] == <span class="vhdllogic">1'b0</span>) ? <span class="vhdlchar">pc</span> + <span class="vhdllogic">32'd2</span> : <span class="vhdlchar">pc</span> + <span class="vhdllogic">32'd4</span>;
<a name="l01747"></a>01747 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">pc_control</span> == <a class="code" href="ao68000_8v.html#a48c2827ab160beae0aab354b09b59e1a">`PC_FROM_PREFETCH_IR</a><span class="vhdlchar"></span>) <span class="vhdlchar">pc</span> = <a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">47</span>:<span class="vhdllogic">16</span>];
<a name="l01748"></a>01748 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">pc_control</span> == <a class="code" href="ao68000_8v.html#a6f1c276d75adca2b0290b7936476fde8">`PC_INCR_BY_2_IN_MAIN_LOOP</a><span class="vhdlchar"></span> && <a class="code" href="classregisters.html#aabb30e872d04701c156a70c4e1e7a3ba">prefetch_ir_valid</a> == <span class="vhdllogic">1'b1</span> && <a class="code" href="classregisters.html#a1444e3b474fdf49e5ab8a0283060ceab">decoder_trap</a> == <span class="vhdllogic">8'd0</span> && <span class="vhdlchar">stop_flag</span> == <span class="vhdllogic">1'b0</span>)
<a name="l01749"></a>01749 <span class="vhdlchar">pc</span> = <span class="vhdlchar">pc</span> + <span class="vhdllogic">32'd2</span>;
<a name="l01750"></a>01750 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">pc</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b0</span>) <a class="code" href="classregisters.html#a87b4409ca50b4ccad122fad79a9d6665">pc_valid</a> <= <span class="vhdlchar">pc</span>;
<a name="l01751"></a>01751 <span class="vhdlkeyword">end</span>
<a name="l01752"></a>01752 <span class="vhdlkeyword">end</span>
</pre></div>
</div>
</div>
<a class="anchor" id="acf180186b03cdc0ad93be0efb7fa2815"></a><!-- doxytag: member="registers::ALWAYS_20" ref="acf180186b03cdc0ad93be0efb7fa2815" args="clock, reset_n" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_20 <td></td>
<td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> , </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> ) </td>
</tr>
<code> [Always Construct]</code></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01962">1962</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
<div class="fragment"><pre class="fragment">
<a name="l01962"></a>01962 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
<a name="l01963"></a>01963 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">group_0_flag</span> <= <span class="vhdllogic">1'b0</span>;
<a name="l01964"></a>01964 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">group_0_flag_control</span> == <a class="code" href="ao68000_8v.html#a5333b31d43f3c7de70d3cad313720ef4">`GROUP_0_FLAG_SET</a><span class="vhdlchar"></span>) <span class="vhdlchar">group_0_flag</span> <= <span class="vhdllogic">1'b1</span>;
<a name="l01965"></a>01965 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">group_0_flag_control</span> == <a class="code" href="ao68000_8v.html#a28adb393ace594d548dfe7f070fd837b">`GROUP_0_FLAG_CLEAR_WHEN_VALID_PREFETCH</a><span class="vhdlchar"></span> && <a class="code" href="classregisters.html#aabb30e872d04701c156a70c4e1e7a3ba">prefetch_ir_valid</a> == <span class="vhdllogic">1'b1</span> && <span class="vhdlchar">stop_flag</span> == <span class="vhdllogic">1'b0</span>)
<a name="l01966"></a>01966 <span class="vhdlchar">group_0_flag</span> <= <span class="vhdllogic">1'b0</span>;
<a name="l01967"></a>01967 <span class="vhdlkeyword">end</span>
</pre></div>
</div>
</div>
<a class="anchor" id="a328ee93f9ab0ed3ebab4dc5936a7c5a0"></a><!-- doxytag: member="registers::ALWAYS_21" ref="a328ee93f9ab0ed3ebab4dc5936a7c5a0" args="clock, reset_n" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
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<td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_21 <td></td>
<td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> , </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> ) </td>
</tr>
<code> [Always Construct]</code></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01969">1969</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
<div class="fragment"><pre class="fragment">
<a name="l01969"></a>01969 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
<a name="l01970"></a>01970 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">instruction_flag</span> <= <span class="vhdllogic">1'b0</span>;
<a name="l01971"></a>01971 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">instruction_flag_control</span> == <a class="code" href="ao68000_8v.html#a6882447365cc7940c16017ee13305875">`INSTRUCTION_FLAG_SET</a><span class="vhdlchar"></span>) <span class="vhdlchar">instruction_flag</span> <= <span class="vhdllogic">1'b1</span>;
<a name="l01972"></a>01972 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">instruction_flag_control</span> == <a class="code" href="ao68000_8v.html#adaf70d0e1aaa9fe89fc79971d67bc172">`INSTRUCTION_FLAG_CLEAR_IN_MAIN_LOOP</a><span class="vhdlchar"></span> && <a class="code" href="classregisters.html#aabb30e872d04701c156a70c4e1e7a3ba">prefetch_ir_valid</a> == <span class="vhdllogic">1'b1</span> && <a class="code" href="classregisters.html#a1444e3b474fdf49e5ab8a0283060ceab">decoder_trap</a> == <span class="vhdllogic">8'd0</span> && <span class="vhdlchar">stop_flag</span> == <span class="vhdllogic">1'b0</span>)
<a name="l01973"></a>01973 <span class="vhdlchar">instruction_flag</span> <= <span class="vhdllogic">1'b0</span>;
<a name="l01974"></a>01974 <span class="vhdlkeyword">end</span>
</pre></div>
</div>
</div>
<a class="anchor" id="ad172a9061d9bb3653a3996dc4a74e101"></a><!-- doxytag: member="registers::ALWAYS_22" ref="ad172a9061d9bb3653a3996dc4a74e101" args="clock, reset_n" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
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<td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_22 <td></td>
<td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> , </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> ) </td>
</tr>
<code> [Always Construct]</code></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01976">1976</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
<div class="fragment"><pre class="fragment">
<a name="l01976"></a>01976 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
<a name="l01977"></a>01977 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">read_modify_write_flag</span> <= <span class="vhdllogic">1'b0</span>;
<a name="l01978"></a>01978 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">read_modify_write_flag_control</span> == <a class="code" href="ao68000_8v.html#a2ba2dbb4697aa9a3559b775da0ade761">`READ_MODIFY_WRITE_FLAG_SET</a><span class="vhdlchar"></span>) <span class="vhdlchar">read_modify_write_flag</span> <= <span class="vhdllogic">1'b1</span>;
<a name="l01979"></a>01979 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">read_modify_write_flag_control</span> == <a class="code" href="ao68000_8v.html#ace5de6cd5ad33427e8efd5ec8191c297">`READ_MODIFY_WRITE_FLAG_CLEAR</a><span class="vhdlchar"></span>) <span class="vhdlchar">read_modify_write_flag</span> <= <span class="vhdllogic">1'b0</span>;
<a name="l01980"></a>01980 <span class="vhdlkeyword">end</span>
</pre></div>
</div>
</div>
<a class="anchor" id="a34326a20d0a44ce95c7da4da53005097"></a><!-- doxytag: member="registers::ALWAYS_23" ref="a34326a20d0a44ce95c7da4da53005097" args="clock, reset_n" -->
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<td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_23 <td></td>
<td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> , </td>
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<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> ) </td>
</tr>
<code> [Always Construct]</code></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01982">1982</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
<div class="fragment"><pre class="fragment">
<a name="l01982"></a>01982 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
<a name="l01983"></a>01983 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">do_reset_flag</span> <= <span class="vhdllogic">1'b0</span>;
<a name="l01984"></a>01984 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_reset_flag_control</span> == <a class="code" href="ao68000_8v.html#a682472d63f131aa31c38abd6f2d577ab">`DO_RESET_FLAG_SET</a><span class="vhdlchar"></span>) <span class="vhdlchar">do_reset_flag</span> <= <span class="vhdllogic">1'b1</span>;
<a name="l01985"></a>01985 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_reset_flag_control</span> == <a class="code" href="ao68000_8v.html#afd7c962bcd95f3629d247e7790f9cf95">`DO_RESET_FLAG_CLEAR</a><span class="vhdlchar"></span>) <span class="vhdlchar">do_reset_flag</span> <= <span class="vhdllogic">1'b0</span>;
<a name="l01986"></a>01986 <span class="vhdlkeyword">end</span>
</pre></div>
</div>
</div>
<a class="anchor" id="ad881b4aebf8b3df42129f9731b6f6098"></a><!-- doxytag: member="registers::ALWAYS_24" ref="ad881b4aebf8b3df42129f9731b6f6098" args="clock, reset_n" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_24 <td></td>
<td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> , </td>
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<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> ) </td>
</tr>
<code> [Always Construct]</code></td>
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</table>
</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01988">1988</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
<div class="fragment"><pre class="fragment">
<a name="l01988"></a>01988 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
<a name="l01989"></a>01989 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">do_interrupt_flag</span> <= <span class="vhdllogic">1'b0</span>;
<a name="l01990"></a>01990 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_interrupt_flag_control</span> == <a class="code" href="ao68000_8v.html#acc420165ae00aa63b4d40c220dc1ed79">`DO_INTERRUPT_FLAG_SET_IF_ACTIVE</a><span class="vhdlchar"></span>) <span class="vhdlchar">do_interrupt_flag</span> <= (<a class="code" href="classregisters.html#aaa89ede670fdc60f2b18c637c50f0dff">interrupt_mask</a> != <span class="vhdllogic">3'b000</span>) ? <span class="vhdllogic">1'b1</span> : <span class="vhdllogic">1'b0</span>;
<a name="l01991"></a>01991 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_interrupt_flag_control</span> == <a class="code" href="ao68000_8v.html#abe668eeea71491f898b31b9c66a4db96">`DO_INTERRUPT_FLAG_CLEAR</a><span class="vhdlchar"></span>) <span class="vhdlchar">do_interrupt_flag</span> <= <span class="vhdllogic">1'b0</span>;
<a name="l01992"></a>01992 <span class="vhdlkeyword">end</span>
</pre></div>
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<a class="anchor" id="aa69b93f001339d4b8ae1295a5cb215ec"></a><!-- doxytag: member="registers::ALWAYS_25" ref="aa69b93f001339d4b8ae1295a5cb215ec" args="clock, reset_n" -->
<div class="memitem">
<div class="memproto">
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<td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_25 <td></td>
<td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> , </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> ) </td>
</tr>
<code> [Always Construct]</code></td>
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</table>
</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01994">1994</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
<div class="fragment"><pre class="fragment">
<a name="l01994"></a>01994 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
<a name="l01995"></a>01995 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">do_read_flag</span> <= <span class="vhdllogic">1'b0</span>;
<a name="l01996"></a>01996 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_read_flag_control</span> == <a class="code" href="ao68000_8v.html#a210a4746c070617bd4272cf091ce4977">`DO_READ_FLAG_SET</a><span class="vhdlchar"></span>) <span class="vhdlchar">do_read_flag</span> <= <span class="vhdllogic">1'b1</span>;
<a name="l01997"></a>01997 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_read_flag_control</span> == <a class="code" href="ao68000_8v.html#a3186ce27b4c9202d124c4bee6b07e2fd">`DO_READ_FLAG_CLEAR</a><span class="vhdlchar"></span>) <span class="vhdlchar">do_read_flag</span> <= <span class="vhdllogic">1'b0</span>;
<a name="l01998"></a>01998 <span class="vhdlkeyword">end</span>
</pre></div>
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<a class="anchor" id="a63d22bb9298a179653d09d6b21e6c68b"></a><!-- doxytag: member="registers::ALWAYS_26" ref="a63d22bb9298a179653d09d6b21e6c68b" args="clock, reset_n" -->
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<td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_26 <td></td>
<td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> , </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> ) </td>
</tr>
<code> [Always Construct]</code></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02000">2000</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
<div class="fragment"><pre class="fragment">
<a name="l02000"></a>02000 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
<a name="l02001"></a>02001 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">do_write_flag</span> <= <span class="vhdllogic">1'b0</span>;
<a name="l02002"></a>02002 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_write_flag_control</span> == <a class="code" href="ao68000_8v.html#a97fc325edc48a555daf24f1757c5e7bf">`DO_WRITE_FLAG_SET</a><span class="vhdlchar"></span>) <span class="vhdlchar">do_write_flag</span> <= <span class="vhdllogic">1'b1</span>;
<a name="l02003"></a>02003 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_write_flag_control</span> == <a class="code" href="ao68000_8v.html#ad6f9aea669c0c0233f4155f29afc4d1d">`DO_WRITE_FLAG_CLEAR</a><span class="vhdlchar"></span>) <span class="vhdlchar">do_write_flag</span> <= <span class="vhdllogic">1'b0</span>;
<a name="l02004"></a>02004 <span class="vhdlkeyword">end</span>
</pre></div>
</div>
</div>
<a class="anchor" id="a66ffba6d56dd08fe7b968605c3b68465"></a><!-- doxytag: member="registers::ALWAYS_27" ref="a66ffba6d56dd08fe7b968605c3b68465" args="clock, reset_n" -->
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<div class="memproto">
<table class="memname">
<tr>
<td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_27 <td></td>
<td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> , </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> ) </td>
</tr>
<code> [Always Construct]</code></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02006">2006</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
<div class="fragment"><pre class="fragment">
<a name="l02006"></a>02006 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
<a name="l02007"></a>02007 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">do_blocked_flag</span> <= <span class="vhdllogic">1'b0</span>;
<a name="l02008"></a>02008 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_blocked_flag_control</span> == <a class="code" href="ao68000_8v.html#ac69029fe984c3090537ed247a8106344">`DO_BLOCKED_FLAG_SET</a><span class="vhdlchar"></span>) <span class="vhdlchar">do_blocked_flag</span> <= <span class="vhdllogic">1'b1</span>;
<a name="l02009"></a>02009 <span class="vhdlkeyword">end</span>
</pre></div>
</div>
</div>
<a class="anchor" id="ab3c53c1dc1763e2d051eaa736e429d58"></a><!-- doxytag: member="registers::ALWAYS_28" ref="ab3c53c1dc1763e2d051eaa736e429d58" args="clock, reset_n" -->
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<div class="memproto">
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<tr>
<td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_28 <td></td>
<td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> , </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> ) </td>
</tr>
<code> [Always Construct]</code></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02011">2011</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
<div class="fragment"><pre class="fragment">
<a name="l02011"></a>02011 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
<a name="l02012"></a>02012 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">data_write</span> <= <span class="vhdllogic">32'd0</span>;
<a name="l02013"></a>02013 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">data_write_control</span> == <a class="code" href="ao68000_8v.html#ab576808298f9e1938241b8843e55c54e">`DATA_WRITE_FROM_RESULT</a><span class="vhdlchar"></span>) <span class="vhdlchar">data_write</span> <= <a class="code" href="classregisters.html#a81ed0f1a7f814e74696bea4db63f1e31">result</a>;
<a name="l02014"></a>02014 <span class="vhdlkeyword">end</span>
</pre></div>
</div>
</div>
<a class="anchor" id="a160e4dadb225ac705317bf8de0c78277"></a><!-- doxytag: member="registers::ALWAYS_3" ref="a160e4dadb225ac705317bf8de0c78277" args="clock, reset_n" -->
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<td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_3 <td></td>
<td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> , </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> ) </td>
</tr>
<code> [Always Construct]</code></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01764">1764</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
<div class="fragment"><pre class="fragment">
<a name="l01764"></a>01764 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
<a name="l01765"></a>01765 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
<a name="l01766"></a>01766 <span class="vhdlchar">size</span> <= <span class="vhdllogic">2'b00</span>;
<a name="l01767"></a>01767 <span class="vhdlkeyword">end</span>
<a name="l01768"></a>01768 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
<a name="l01769"></a>01769 <span class="keyword">// BYTE</span>
<a name="l01770"></a>01770 <span class="vhdlchar">size</span>[<span class="vhdllogic">0</span>] <= (<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a8a04b85bed76a4381d1187aec9694a7e">`SIZE_BYTE</a><span class="vhdlchar"></span>)
<a name="l01771"></a>01771 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#ad8d417f0548efb4299bed1ed75004cbe">`SIZE_3</a><span class="vhdlchar"></span>) && (<span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b00</span>))
<a name="l01772"></a>01772 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a4d9196508aad9e995d45bfda3f7c6884">`SIZE_4</a><span class="vhdlchar"></span>) && (<span class="vhdlchar">ir</span>[<span class="vhdllogic">13</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">2'b01</span>))
<a name="l01773"></a>01773 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a3ce4d5e820fe7c438d0bd9c7f067ac3f">`SIZE_6</a><span class="vhdlchar"></span>) && (<span class="vhdlchar">ir</span>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b000</span>));
<a name="l01774"></a>01774 <span class="keyword">// WORD</span>
<a name="l01775"></a>01775 <span class="vhdlchar">size</span>[<span class="vhdllogic">1</span>] <= (<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a9da3fa515a6d6e5949573714c5682999">`SIZE_WORD</a><span class="vhdlchar"></span>)
<a name="l01776"></a>01776 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a1b8724879ab643802f27348fa58f7208">`SIZE_1</a><span class="vhdlchar"></span>) && (<span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b00</span>))
<a name="l01777"></a>01777 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a83d20a891b85a7fabe3d8c74b66ad884">`SIZE_1_PLUS</a><span class="vhdlchar"></span>) && (<span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b10</span>))
<a name="l01778"></a>01778 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a1eca0e7e9287916bcfa96b96b0c46154">`SIZE_2</a><span class="vhdlchar"></span>) && (<span class="vhdlchar">ir</span>[<span class="vhdllogic">6</span>] == <span class="vhdllogic">1'b0</span>))
<a name="l01779"></a>01779 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#ad8d417f0548efb4299bed1ed75004cbe">`SIZE_3</a><span class="vhdlchar"></span>) && (<span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b01</span>))
<a name="l01780"></a>01780 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a4d9196508aad9e995d45bfda3f7c6884">`SIZE_4</a><span class="vhdlchar"></span>) && (<span class="vhdlchar">ir</span>[<span class="vhdllogic">13</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">2'b11</span>))
<a name="l01781"></a>01781 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a0e07cba66f352b53ebb2dd2a48c58cff">`SIZE_5</a><span class="vhdlchar"></span>) && (<span class="vhdlchar">ir</span>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b0</span>));
<a name="l01782"></a>01782 <span class="keyword">// LONG</span>
<a name="l01783"></a>01783 <span class="vhdlchar">size</span>[<span class="vhdllogic">2</span>] <= (<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#ae54bb350f5d3a019211af2a214f46273">`SIZE_LONG</a><span class="vhdlchar"></span>)
<a name="l01784"></a>01784 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a1b8724879ab643802f27348fa58f7208">`SIZE_1</a><span class="vhdlchar"></span>) && (<span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b00</span>))
<a name="l01785"></a>01785 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a83d20a891b85a7fabe3d8c74b66ad884">`SIZE_1_PLUS</a><span class="vhdlchar"></span>) && (<span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b10</span>))
<a name="l01786"></a>01786 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a1eca0e7e9287916bcfa96b96b0c46154">`SIZE_2</a><span class="vhdlchar"></span>) && (<span class="vhdlchar">ir</span>[<span class="vhdllogic">6</span>] == <span class="vhdllogic">1'b1</span>))
<a name="l01787"></a>01787 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#ad8d417f0548efb4299bed1ed75004cbe">`SIZE_3</a><span class="vhdlchar"></span>) && (<span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>] == <span class="vhdllogic">1'b1</span>))
<a name="l01788"></a>01788 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a4d9196508aad9e995d45bfda3f7c6884">`SIZE_4</a><span class="vhdlchar"></span>) && (<span class="vhdlchar">ir</span>[<span class="vhdllogic">12</span>] == <span class="vhdllogic">1'b0</span>))
<a name="l01789"></a>01789 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a0e07cba66f352b53ebb2dd2a48c58cff">`SIZE_5</a><span class="vhdlchar"></span>) && (<span class="vhdlchar">ir</span>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b1</span>))
<a name="l01790"></a>01790 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a3ce4d5e820fe7c438d0bd9c7f067ac3f">`SIZE_6</a><span class="vhdlchar"></span>) && (<span class="vhdlchar">ir</span>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b000</span>));
<a name="l01791"></a>01791 <span class="vhdlkeyword">end</span>
<a name="l01792"></a>01792 <span class="vhdlkeyword">end</span>
</pre></div>
</div>
</div>
<a class="anchor" id="a098bb8c5f886c173a49d1e015dd37289"></a><!-- doxytag: member="registers::ALWAYS_4" ref="a098bb8c5f886c173a49d1e015dd37289" args="clock, reset_n" -->
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<table class="memname">
<tr>
<td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_4 <td></td>
<td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> , </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> ) </td>
</tr>
<code> [Always Construct]</code></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01794">1794</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
<div class="fragment"><pre class="fragment">
<a name="l01794"></a>01794 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
<a name="l01795"></a>01795 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <a class="code" href="classregisters.html#a69652ae311e16ddcb1bb0dbc90744156">ea_reg</a> <= <span class="vhdllogic">3'b000</span>;
<a name="l01796"></a>01796 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a87fed6b8d7f55252c49ab2fc43d39d9a">ea_reg_control</a> == <a class="code" href="ao68000_8v.html#ab608c5385657295b902b8ffc21c43d03">`EA_REG_IR_2_0</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a69652ae311e16ddcb1bb0dbc90744156">ea_reg</a> <= <span class="vhdlchar">ir</span>[<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>];
<a name="l01797"></a>01797 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a87fed6b8d7f55252c49ab2fc43d39d9a">ea_reg_control</a> == <a class="code" href="ao68000_8v.html#a56f29ecaaf69843219c88d8e0f252048">`EA_REG_IR_11_9</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a69652ae311e16ddcb1bb0dbc90744156">ea_reg</a> <= <span class="vhdlchar">ir</span>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>];
<a name="l01798"></a>01798 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a87fed6b8d7f55252c49ab2fc43d39d9a">ea_reg_control</a> == <a class="code" href="ao68000_8v.html#af2b8ce7c793c79dee8394ad309a1ef71">`EA_REG_MOVEM_REG_2_0</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a69652ae311e16ddcb1bb0dbc90744156">ea_reg</a> <= <span class="vhdlchar">movem_modreg</span>[<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>];
<a name="l01799"></a>01799 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a87fed6b8d7f55252c49ab2fc43d39d9a">ea_reg_control</a> == <a class="code" href="ao68000_8v.html#aa5ef414e1c0f769a38cdd8b3aeef5184">`EA_REG_3b111</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a69652ae311e16ddcb1bb0dbc90744156">ea_reg</a> <= <span class="vhdllogic">3'b111</span>;
<a name="l01800"></a>01800 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a87fed6b8d7f55252c49ab2fc43d39d9a">ea_reg_control</a> == <a class="code" href="ao68000_8v.html#ab4936576a8613273a6487d2b78812c55">`EA_REG_3b100</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a69652ae311e16ddcb1bb0dbc90744156">ea_reg</a> <= <span class="vhdllogic">3'b100</span>;
<a name="l01801"></a>01801 <span class="vhdlkeyword">end</span>
</pre></div>
</div>
</div>
<a class="anchor" id="a6fc98500064486297076cc7c8e99e16f"></a><!-- doxytag: member="registers::ALWAYS_5" ref="a6fc98500064486297076cc7c8e99e16f" args="clock, reset_n" -->
<div class="memitem">
<div class="memproto">
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<tr>
<td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_5 <td></td>
<td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> , </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> ) </td>
</tr>
<code> [Always Construct]</code></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01803">1803</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
<div class="fragment"><pre class="fragment">
<a name="l01803"></a>01803 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
<a name="l01804"></a>01804 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= <span class="vhdllogic">3'b000</span>;
<a name="l01805"></a>01805 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#a0c094175d5b6718611708b08af5e6342">`EA_MOD_IR_5_3</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= <span class="vhdlchar">ir</span>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>];
<a name="l01806"></a>01806 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#a45b520ba3dd813510ddca0ebe0a652f4">`EA_MOD_MOVEM_MOD_5_3</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= <span class="vhdlchar">movem_modreg</span>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>];
<a name="l01807"></a>01807 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#a46d304e545e3f136f9bc7fe83ffe61df">`EA_MOD_IR_8_6</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= <span class="vhdlchar">ir</span>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>];
<a name="l01808"></a>01808 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#a2e15ad20aa0f28ef9042982260a21316">`EA_MOD_PREDEC</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= <span class="vhdllogic">3'b100</span>;
<a name="l01809"></a>01809 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#ae4ecbd320f11539d132c8e6aa3fdcb5c">`EA_MOD_3b111</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= <span class="vhdllogic">3'b111</span>;
<a name="l01810"></a>01810 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#aee18d2c3a30bdec23a7de0889deb0d94">`EA_MOD_DN_PREDEC</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= (<span class="vhdlchar">ir</span>[<span class="vhdllogic">3</span>] == <span class="vhdllogic">1'b0</span>) ? <span class="keyword">/* Dn **/</span> <span class="vhdllogic">3'b000</span> : <span class="keyword">/* -(An) **/</span> <span class="vhdllogic">3'b100</span>;
<a name="l01811"></a>01811 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#ac190b9646213ddb87ec06a5858d479b3">`EA_MOD_DN_AN_EXG</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= (<span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">5'b01000</span> || <span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">5'b10001</span>) ? <span class="keyword">/* Dn **/</span> <span class="vhdllogic">3'b000</span> : <span class="keyword">/* An **/</span> <span class="vhdllogic">3'b001</span>;
<a name="l01812"></a>01812 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#a51a36024571aca1d7d7c7fa928956589">`EA_MOD_POSTINC</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= <span class="vhdllogic">3'b011</span>;
<a name="l01813"></a>01813 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#a7a6ccf87a21e66605e4672e95a6578e4">`EA_MOD_AN</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= <span class="vhdllogic">3'b001</span>;
<a name="l01814"></a>01814 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#a8a000a242ea6cc51ac97ec35753faf7b">`EA_MOD_DN</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= <span class="vhdllogic">3'b000</span>;
<a name="l01815"></a>01815 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#a88ded717145b6f89a3cd3416577225f0">`EA_MOD_INDIRECTOFFSET</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= <span class="vhdllogic">3'b101</span>;
<a name="l01816"></a>01816 <span class="vhdlkeyword">end</span>
</pre></div>
</div>
</div>
<a class="anchor" id="aa536be1ed88148e7c828c0183e8a0757"></a><!-- doxytag: member="registers::ALWAYS_6" ref="aa536be1ed88148e7c828c0183e8a0757" args="clock, reset_n" -->
<div class="memitem">
<div class="memproto">
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<td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_6 <td></td>
<td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> , </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> ) </td>
</tr>
<code> [Always Construct]</code></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01818">1818</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
<div class="fragment"><pre class="fragment">
<a name="l01818"></a>01818 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
<a name="l01819"></a>01819 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <a class="code" href="classregisters.html#a531a4ea89d5bde45780adeeda7d42bb4">ea_type</a> <= <a class="code" href="ao68000_8v.html#a30b69aee8fb5af4ab38fc9f0d92a28d3">`EA_TYPE_IDLE</a><span class="vhdlchar"></span>;
<a name="l01820"></a>01820 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a6fe315cf4e9805733719db71cf630847">ea_type_control</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a531a4ea89d5bde45780adeeda7d42bb4">ea_type</a> <= <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span>;
<a name="l01821"></a>01821 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a6fe315cf4e9805733719db71cf630847">ea_type_control</a> == <a class="code" href="ao68000_8v.html#a925f0004ba49b82dbdf7c4ae969ba6ed">`EA_TYPE_CONTROL_POSTINC</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a531a4ea89d5bde45780adeeda7d42bb4">ea_type</a> <= <a class="code" href="ao68000_8v.html#a925f0004ba49b82dbdf7c4ae969ba6ed">`EA_TYPE_CONTROL_POSTINC</a><span class="vhdlchar"></span>;
<a name="l01822"></a>01822 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a6fe315cf4e9805733719db71cf630847">ea_type_control</a> == <a class="code" href="ao68000_8v.html#a41499eaa1b7aa62f455a07e5435d754a">`EA_TYPE_CONTROLALTER_PREDEC</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a531a4ea89d5bde45780adeeda7d42bb4">ea_type</a> <= <a class="code" href="ao68000_8v.html#a41499eaa1b7aa62f455a07e5435d754a">`EA_TYPE_CONTROLALTER_PREDEC</a><span class="vhdlchar"></span>;
<a name="l01823"></a>01823 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a6fe315cf4e9805733719db71cf630847">ea_type_control</a> == <a class="code" href="ao68000_8v.html#ae2c794f81236993a23138cbf3f7eda44">`EA_TYPE_CONTROL</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a531a4ea89d5bde45780adeeda7d42bb4">ea_type</a> <= <a class="code" href="ao68000_8v.html#ae2c794f81236993a23138cbf3f7eda44">`EA_TYPE_CONTROL</a><span class="vhdlchar"></span>;
<a name="l01824"></a>01824 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a6fe315cf4e9805733719db71cf630847">ea_type_control</a> == <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a531a4ea89d5bde45780adeeda7d42bb4">ea_type</a> <= <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span>;
<a name="l01825"></a>01825 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a6fe315cf4e9805733719db71cf630847">ea_type_control</a> == <a class="code" href="ao68000_8v.html#a8e7bc745d4def25f5a995a6955dbdb4b">`EA_TYPE_DN_AN</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a531a4ea89d5bde45780adeeda7d42bb4">ea_type</a> <= <a class="code" href="ao68000_8v.html#a8e7bc745d4def25f5a995a6955dbdb4b">`EA_TYPE_DN_AN</a><span class="vhdlchar"></span>;
<a name="l01826"></a>01826 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a6fe315cf4e9805733719db71cf630847">ea_type_control</a> == <a class="code" href="ao68000_8v.html#a653530f090b85ba7bcd93912b8834412">`EA_TYPE_MEMORYALTER</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a531a4ea89d5bde45780adeeda7d42bb4">ea_type</a> <= <a class="code" href="ao68000_8v.html#a653530f090b85ba7bcd93912b8834412">`EA_TYPE_MEMORYALTER</a><span class="vhdlchar"></span>;
<a name="l01827"></a>01827 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a6fe315cf4e9805733719db71cf630847">ea_type_control</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a531a4ea89d5bde45780adeeda7d42bb4">ea_type</a> <= <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>;
<a name="l01828"></a>01828 <span class="vhdlkeyword">end</span>
</pre></div>
</div>
</div>
<a class="anchor" id="a8fa9503b229756474eafc4b087aa6511"></a><!-- doxytag: member="registers::ALWAYS_7" ref="a8fa9503b229756474eafc4b087aa6511" args="clock, reset_n" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_7 <td></td>
<td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> , </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> ) </td>
</tr>
<code> [Always Construct]</code></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01830">1830</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
<div class="fragment"><pre class="fragment">
<a name="l01830"></a>01830 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
<a name="l01831"></a>01831 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= <span class="vhdllogic">32'hFFFFFFFF</span>;
<a name="l01832"></a>01832 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#a29e287eda5813f253f9f1cd527021533">`OP1_FROM_OP2</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= <span class="vhdlchar">operand2</span>;
<a name="l01833"></a>01833 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#ab601cf0d52e5fe6ae155ab8084b236e1">`OP1_FROM_ADDRESS</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= <span class="vhdlchar">address</span>;
<a name="l01834"></a>01834 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#aec7f41507eab6c659f5d544c942b441e">`OP1_FROM_DATA</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <=
<a name="l01835"></a>01835 (<span class="vhdlchar">size</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) ? { {<span class="vhdllogic">24</span>{<a class="code" href="classregisters.html#a015db9817045d85028931bbb036f7b59">data_read</a>[<span class="vhdllogic">7</span>]}}, <a class="code" href="classregisters.html#a015db9817045d85028931bbb036f7b59">data_read</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] } :
<a name="l01836"></a>01836 (<span class="vhdlchar">size</span>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) ? { {<span class="vhdllogic">16</span>{<a class="code" href="classregisters.html#a015db9817045d85028931bbb036f7b59">data_read</a>[<span class="vhdllogic">15</span>]}}, <a class="code" href="classregisters.html#a015db9817045d85028931bbb036f7b59">data_read</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] } :
<a name="l01837"></a>01837 <a class="code" href="classregisters.html#a015db9817045d85028931bbb036f7b59">data_read</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
<a name="l01838"></a>01838 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#abc0874c9141535c9c6a071653810c8fc">`OP1_FROM_IMMEDIATE</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <=
<a name="l01839"></a>01839 (<span class="vhdlchar">size</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) ? { {<span class="vhdllogic">24</span>{<a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">71</span>]}}, <a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">71</span>:<span class="vhdllogic">64</span>] } :
<a name="l01840"></a>01840 (<span class="vhdlchar">size</span>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) ? { {<span class="vhdllogic">16</span>{<a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">79</span>]}}, <a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">79</span>:<span class="vhdllogic">64</span>] } :
<a name="l01841"></a>01841 <a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">79</span>:<span class="vhdllogic">48</span>];
<a name="l01842"></a>01842 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#a2adbf20e4776f4f5449563560fcfea3e">`OP1_FROM_RESULT</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= <a class="code" href="classregisters.html#a81ed0f1a7f814e74696bea4db63f1e31">result</a>;
<a name="l01843"></a>01843 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#ac2bd7be96e464a7a06affeb71024f266">`OP1_MOVEQ</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= { {<span class="vhdllogic">24</span>{<span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>]}}, <span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] };
<a name="l01844"></a>01844 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#aade66d4090f1aea9ed568a4e17ff1eae">`OP1_FROM_PC</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= <a class="code" href="classregisters.html#a87b4409ca50b4ccad122fad79a9d6665">pc_valid</a>;
<a name="l01845"></a>01845 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#a4db6f8d952dd7d7cfffeb0de4ad4a08b">`OP1_LOAD_ZEROS</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= <span class="vhdllogic">32'b0</span>;
<a name="l01846"></a>01846 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#ae8489ec12e458975d614347191ba2004">`OP1_LOAD_ONES</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= <span class="vhdllogic">32'hFFFFFFFF</span>;
<a name="l01847"></a>01847 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#a9e1d49d77f5b144fff6cc8c0c021e5d2">`OP1_FROM_SR</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= { <span class="vhdllogic">16'b0</span>, <a class="code" href="classregisters.html#ad583f99f893a13448ecd261e637ad56b">sr</a>[<span class="vhdllogic">15</span>], <span class="vhdllogic">1'b0</span>, <a class="code" href="classregisters.html#ad583f99f893a13448ecd261e637ad56b">sr</a>[<span class="vhdllogic">13</span>], <span class="vhdllogic">2'b0</span>, <a class="code" href="classregisters.html#ad583f99f893a13448ecd261e637ad56b">sr</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">8</span>], <span class="vhdllogic">3'b0</span>, <a class="code" href="classregisters.html#ad583f99f893a13448ecd261e637ad56b">sr</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">0</span>] };
<a name="l01848"></a>01848 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#a1a44c33265ec779ad10e437621cda43b">`OP1_FROM_USP</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= <a class="code" href="classregisters.html#ae8312cd504b37ae6dc199537ddf93bcb">usp</a>;
<a name="l01849"></a>01849 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#a4900ac90de9fd53eaeb1acddf51a9008">`OP1_FROM_AN</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <=
<a name="l01850"></a>01850 (<span class="vhdlchar">size</span>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) ? { {<span class="vhdllogic">16</span>{<a class="code" href="classregisters.html#a4076832588fccdd9d5d0cc1b4b8dd0b0">An_output</a>[<span class="vhdllogic">15</span>]}}, <a class="code" href="classregisters.html#a4076832588fccdd9d5d0cc1b4b8dd0b0">An_output</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] } :
<a name="l01851"></a>01851 <a class="code" href="classregisters.html#a4076832588fccdd9d5d0cc1b4b8dd0b0">An_output</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
<a name="l01852"></a>01852 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#a3aa722db3503e9370be36b3d409f3e17">`OP1_FROM_DN</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <=
<a name="l01853"></a>01853 (<span class="vhdlchar">size</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) ? { {<span class="vhdllogic">24</span>{<a class="code" href="classregisters.html#a0376be737f05fcad48a8057caa2f1fcf">Dn_output</a>[<span class="vhdllogic">7</span>]}}, <a class="code" href="classregisters.html#a0376be737f05fcad48a8057caa2f1fcf">Dn_output</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] } :
<a name="l01854"></a>01854 (<span class="vhdlchar">size</span>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) ? { {<span class="vhdllogic">16</span>{<a class="code" href="classregisters.html#a0376be737f05fcad48a8057caa2f1fcf">Dn_output</a>[<span class="vhdllogic">15</span>]}}, <a class="code" href="classregisters.html#a0376be737f05fcad48a8057caa2f1fcf">Dn_output</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] } :
<a name="l01855"></a>01855 <a class="code" href="classregisters.html#a0376be737f05fcad48a8057caa2f1fcf">Dn_output</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
<a name="l01856"></a>01856 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#a083db35259f035ab10f606d2c7dd82c6">`OP1_FROM_IR</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= { <span class="vhdllogic">16'b0</span>, <span class="vhdlchar">ir</span>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] };
<a name="l01857"></a>01857 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#a707f0ca7fa1a08446ba113ede9d5d8a4">`OP1_FROM_FAULT_ADDRESS</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= <a class="code" href="classregisters.html#a2975efdebb48903a858f0558c58d31c2">fault_address_state</a>;
<a name="l01858"></a>01858 <span class="vhdlkeyword">end</span>
</pre></div>
</div>
</div>
<a class="anchor" id="ae6143c84411ad159cbe1662f3909e726"></a><!-- doxytag: member="registers::ALWAYS_8" ref="ae6143c84411ad159cbe1662f3909e726" args="clock, reset_n" -->
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<table class="memname">
<tr>
<td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_8 <td></td>
<td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> , </td>
</tr>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> ) </td>
</tr>
<code> [Always Construct]</code></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01860">1860</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
<div class="fragment"><pre class="fragment">
<a name="l01860"></a>01860 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
<a name="l01861"></a>01861 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">operand2</span> <= <span class="vhdllogic">32'hFFFFFFFF</span>;
<a name="l01862"></a>01862 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand2_control</span> == <a class="code" href="ao68000_8v.html#a092ca695ecfa2de9e4d4a27bbd89d40f">`OP2_FROM_OP1</a><span class="vhdlchar"></span>) <span class="vhdlchar">operand2</span> <= <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a>;
<a name="l01863"></a>01863 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand2_control</span> == <a class="code" href="ao68000_8v.html#a5c2c8ed577b6ab91a5ae3861643575e7">`OP2_LOAD_1</a><span class="vhdlchar"></span>) <span class="vhdlchar">operand2</span> <= <span class="vhdllogic">32'd1</span>;
<a name="l01864"></a>01864 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand2_control</span> == <a class="code" href="ao68000_8v.html#a7c904b70c2347aaee330105f74a69fc1">`OP2_LOAD_COUNT</a><span class="vhdlchar"></span>) <span class="vhdlchar">operand2</span> <=
<a name="l01865"></a>01865 (<span class="vhdlchar">ir</span>[<span class="vhdllogic">5</span>] == <span class="vhdllogic">1'b0</span>) ? ( (<span class="vhdlchar">ir</span>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b000</span>) ? <span class="vhdllogic">32'b1000</span> : { <span class="vhdllogic">29'b0</span>, <span class="vhdlchar">ir</span>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] } ) :
<a name="l01866"></a>01866 { <span class="vhdllogic">26'b0</span>, <span class="vhdlchar">operand2</span>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] };
<a name="l01867"></a>01867 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand2_control</span> == <a class="code" href="ao68000_8v.html#aacec01f4da467eb6785c611710c1219d">`OP2_ADDQ_SUBQ</a><span class="vhdlchar"></span>) <span class="vhdlchar">operand2</span> <= (<span class="vhdlchar">ir</span>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b000</span>) ? <span class="vhdllogic">32'b1000</span> : { <span class="vhdllogic">29'b0</span>, <span class="vhdlchar">ir</span>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] };
<a name="l01868"></a>01868 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand2_control</span> == <a class="code" href="ao68000_8v.html#ad8cdca7f0cbac16e09b4e1a1e3ab4f11">`OP2_MOVE_OFFSET</a><span class="vhdlchar"></span>) <span class="vhdlchar">operand2</span> <= (<span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">8'b0</span>) ? <span class="vhdlchar">operand2</span>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] : { {<span class="vhdllogic">24</span>{<span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>]}}, <span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] };
<a name="l01869"></a>01869 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand2_control</span> == <a class="code" href="ao68000_8v.html#a041be53a35bc1a415713d34c839c81c5">`OP2_MOVE_ADDRESS_BUS_INFO</a><span class="vhdlchar"></span>) <span class="vhdlchar">operand2</span> <= { <span class="vhdllogic">16'b0</span>, <span class="vhdllogic">11'b0</span>, <a class="code" href="classregisters.html#a881b6927205941e0691b73906a7cfdd9">rw_state</a>, <span class="vhdlchar">instruction_flag</span>, <a class="code" href="classregisters.html#af336bd0ea96aad806fdb36dcd673a9c2">fc_state</a>};
<a name="l01870"></a>01870 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand2_control</span> == <a class="code" href="ao68000_8v.html#a81d303d3fcf43bd2ed3b99072571f816">`OP2_DECR_BY_1</a><span class="vhdlchar"></span>) <span class="vhdlchar">operand2</span> <= <span class="vhdlchar">operand2</span> - <span class="vhdllogic">32'b1</span>;
<a name="l01871"></a>01871 <span class="vhdlkeyword">end</span>
</pre></div>
</div>
</div>
<a class="anchor" id="ae04888e60d745f9f64ca5c52d0969adb"></a><!-- doxytag: member="registers::ALWAYS_9" ref="ae04888e60d745f9f64ca5c52d0969adb" args="clock, reset_n" -->
<div class="memitem">
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<td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_9 <td></td>
<td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> , </td>
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<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> ) </td>
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<code> [Always Construct]</code></td>
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</table>
</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01873">1873</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
<div class="fragment"><pre class="fragment">
<a name="l01873"></a>01873 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
<a name="l01874"></a>01874 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">address</span> <= <span class="vhdllogic">32'b0</span>;
<a name="l01875"></a>01875 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#a864e0b06304816dec2d4658503d97495">`ADDRESS_INCR_BY_SIZE</a><span class="vhdlchar"></span>) <span class="vhdlchar">address</span> <= ((<span class="vhdlchar">size</span>[<span class="vhdllogic">0</span>]) && <a class="code" href="classregisters.html#a69652ae311e16ddcb1bb0dbc90744156">ea_reg</a> == <span class="vhdllogic">3'b111</span>) ? <span class="vhdlchar">address</span> + <span class="vhdllogic">32'd2</span> : <span class="vhdlchar">address</span> + {<span class="vhdllogic">29'd0</span>,<span class="vhdlchar">size</span>};
<a name="l01876"></a>01876 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#aa479827c57933eb9ff03788bbe9d6e3a">`ADDRESS_DECR_BY_SIZE</a><span class="vhdlchar"></span>) <span class="vhdlchar">address</span> <= ((<span class="vhdlchar">size</span>[<span class="vhdllogic">0</span>]) && <a class="code" href="classregisters.html#a69652ae311e16ddcb1bb0dbc90744156">ea_reg</a> == <span class="vhdllogic">3'b111</span>) ? <span class="vhdlchar">address</span> - <span class="vhdllogic">32'd2</span> : <span class="vhdlchar">address</span> - {<span class="vhdllogic">29'd0</span>,<span class="vhdlchar">size</span>};
<a name="l01877"></a>01877 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#ac4044068e496c3393c6336b72873a958">`ADDRESS_INCR_BY_2</a><span class="vhdlchar"></span>) <span class="vhdlchar">address</span> <= <span class="vhdlchar">address</span> + <span class="vhdllogic">32'd2</span>;
<a name="l01878"></a>01878 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#afc15ad5da6b4afd71eb879476c603fe3">`ADDRESS_FROM_AN_OUTPUT</a><span class="vhdlchar"></span>) <span class="vhdlchar">address</span> <= <a class="code" href="classregisters.html#a4076832588fccdd9d5d0cc1b4b8dd0b0">An_output</a>;
<a name="l01879"></a>01879 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#ac1143ff5a059fc5609c9419fcd402ae1">`ADDRESS_FROM_BASE_INDEX_OFFSET</a><span class="vhdlchar"></span>) <span class="vhdlchar">address</span> <= <span class="vhdlchar">address</span> + <span class="vhdlchar">index</span> + <span class="vhdlchar">offset</span>;
<a name="l01880"></a>01880 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#aa6ba908e680fe87e46ac1cf014eed463">`ADDRESS_FROM_IMM_16</a><span class="vhdlchar"></span>) <span class="vhdlchar">address</span> <= { {<span class="vhdllogic">16</span>{<a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">79</span>]}}, <a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">79</span>:<span class="vhdllogic">64</span>] };
<a name="l01881"></a>01881 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#aa688332c940cad3a10561a5c9f74698a">`ADDRESS_FROM_IMM_32</a><span class="vhdlchar"></span>) <span class="vhdlchar">address</span> <= <a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">79</span>:<span class="vhdllogic">48</span>];
<a name="l01882"></a>01882 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#aa7a6ef5c21bbbf8a3c5a0437bdda3c85">`ADDRESS_FROM_PC_INDEX_OFFSET</a><span class="vhdlchar"></span>) <span class="vhdlchar">address</span> <= <a class="code" href="classregisters.html#a87b4409ca50b4ccad122fad79a9d6665">pc_valid</a> + <span class="vhdlchar">index</span> + <span class="vhdlchar">offset</span>;
<a name="l01883"></a>01883 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#a2a30a0ecfa48e96cc5be837e7db71cab">`ADDRESS_FROM_TRAP</a><span class="vhdlchar"></span>) <span class="vhdlchar">address</span> <= {<span class="vhdllogic">22'b0</span>, <span class="vhdlchar">trap</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">2'b0</span>};
<a name="l01884"></a>01884 <span class="vhdlkeyword">end</span>
</pre></div>
</div>
</div>
<hr/><h2>Member Data Documentation</h2>
<a class="anchor" id="addbaa332878673f1c1192d8c2c9cd83e"></a><!-- doxytag: member="registers::clock" ref="addbaa332878673f1c1192d8c2c9cd83e" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01621">1621</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
</div>
</div>
<a class="anchor" id="a7e3a00b7da8ae2fbd8336c34673c64a8"></a><!-- doxytag: member="registers::reset_n" ref="a7e3a00b7da8ae2fbd8336c34673c64a8" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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</table>
</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01622">1622</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
</div>
</div>
<a class="anchor" id="a015db9817045d85028931bbb036f7b59"></a><!-- doxytag: member="registers::data_read" ref="a015db9817045d85028931bbb036f7b59" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#a015db9817045d85028931bbb036f7b59">data_read</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01624">1624</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
</div>
</div>
<a class="anchor" id="aa8289dc94534500e03ff980b25804982"></a><!-- doxytag: member="registers::prefetch_ir" ref="aa8289dc94534500e03ff980b25804982" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">79</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01625">1625</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
</div>
</div>
<a class="anchor" id="aabb30e872d04701c156a70c4e1e7a3ba"></a><!-- doxytag: member="registers::prefetch_ir_valid" ref="aabb30e872d04701c156a70c4e1e7a3ba" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#aabb30e872d04701c156a70c4e1e7a3ba">prefetch_ir_valid</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01626">1626</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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</div>
<a class="anchor" id="a81ed0f1a7f814e74696bea4db63f1e31"></a><!-- doxytag: member="registers::result" ref="a81ed0f1a7f814e74696bea4db63f1e31" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#a81ed0f1a7f814e74696bea4db63f1e31">result</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01627">1627</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
</div>
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<a class="anchor" id="ad583f99f893a13448ecd261e637ad56b"></a><!-- doxytag: member="registers::sr" ref="ad583f99f893a13448ecd261e637ad56b" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#ad583f99f893a13448ecd261e637ad56b">sr</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">15</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01628">1628</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
</div>
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<a class="anchor" id="a881b6927205941e0691b73906a7cfdd9"></a><!-- doxytag: member="registers::rw_state" ref="a881b6927205941e0691b73906a7cfdd9" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#a881b6927205941e0691b73906a7cfdd9">rw_state</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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</table>
</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01629">1629</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
</div>
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<a class="anchor" id="af336bd0ea96aad806fdb36dcd673a9c2"></a><!-- doxytag: member="registers::fc_state" ref="af336bd0ea96aad806fdb36dcd673a9c2" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#af336bd0ea96aad806fdb36dcd673a9c2">fc_state</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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</table>
</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01630">1630</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
</div>
</div>
<a class="anchor" id="a2975efdebb48903a858f0558c58d31c2"></a><!-- doxytag: member="registers::fault_address_state" ref="a2975efdebb48903a858f0558c58d31c2" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#a2975efdebb48903a858f0558c58d31c2">fault_address_state</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01631">1631</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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</div>
<a class="anchor" id="ad7009ed104b0324325f2ebe297edc9b4"></a><!-- doxytag: member="registers::interrupt_trap" ref="ad7009ed104b0324325f2ebe297edc9b4" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#ad7009ed104b0324325f2ebe297edc9b4">interrupt_trap</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">7</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01632">1632</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="aaa89ede670fdc60f2b18c637c50f0dff"></a><!-- doxytag: member="registers::interrupt_mask" ref="aaa89ede670fdc60f2b18c637c50f0dff" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#aaa89ede670fdc60f2b18c637c50f0dff">interrupt_mask</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01633">1633</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a1444e3b474fdf49e5ab8a0283060ceab"></a><!-- doxytag: member="registers::decoder_trap" ref="a1444e3b474fdf49e5ab8a0283060ceab" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#a1444e3b474fdf49e5ab8a0283060ceab">decoder_trap</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">7</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01634">1634</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="ae8312cd504b37ae6dc199537ddf93bcb"></a><!-- doxytag: member="registers::usp" ref="ae8312cd504b37ae6dc199537ddf93bcb" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#ae8312cd504b37ae6dc199537ddf93bcb">usp</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01636">1636</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a0376be737f05fcad48a8057caa2f1fcf"></a><!-- doxytag: member="registers::Dn_output" ref="a0376be737f05fcad48a8057caa2f1fcf" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#a0376be737f05fcad48a8057caa2f1fcf">Dn_output</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01637">1637</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a4076832588fccdd9d5d0cc1b4b8dd0b0"></a><!-- doxytag: member="registers::An_output" ref="a4076832588fccdd9d5d0cc1b4b8dd0b0" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#a4076832588fccdd9d5d0cc1b4b8dd0b0">An_output</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01638">1638</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a73560eea6b21f10073a1131e3cffa801"></a><!-- doxytag: member="registers::pc_change" ref="a73560eea6b21f10073a1131e3cffa801" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#a73560eea6b21f10073a1131e3cffa801">pc_change</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">1</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01640">1640</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a69652ae311e16ddcb1bb0dbc90744156"></a><!-- doxytag: member="registers::ea_reg" ref="a69652ae311e16ddcb1bb0dbc90744156" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#a69652ae311e16ddcb1bb0dbc90744156">ea_reg</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01642">1642</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a87fed6b8d7f55252c49ab2fc43d39d9a"></a><!-- doxytag: member="registers::ea_reg_control" ref="a87fed6b8d7f55252c49ab2fc43d39d9a" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#a87fed6b8d7f55252c49ab2fc43d39d9a">ea_reg_control</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01643">1643</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="aafe87b4d917fd589612b82802a4c838b"></a><!-- doxytag: member="registers::ea_mod" ref="aafe87b4d917fd589612b82802a4c838b" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01645">1645</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="ab630b141208b16db686f800d53dc41eb"></a><!-- doxytag: member="registers::ea_mod_control" ref="ab630b141208b16db686f800d53dc41eb" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01646">1646</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a531a4ea89d5bde45780adeeda7d42bb4"></a><!-- doxytag: member="registers::ea_type" ref="a531a4ea89d5bde45780adeeda7d42bb4" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#a531a4ea89d5bde45780adeeda7d42bb4">ea_type</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01648">1648</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a6fe315cf4e9805733719db71cf630847"></a><!-- doxytag: member="registers::ea_type_control" ref="a6fe315cf4e9805733719db71cf630847" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#a6fe315cf4e9805733719db71cf630847">ea_type_control</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01649">1649</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a6d53621114d007f65c3159fd3cad4ea1"></a><!-- doxytag: member="registers::operand1" ref="a6d53621114d007f65c3159fd3cad4ea1" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01652">1652</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a87b4409ca50b4ccad122fad79a9d6665"></a><!-- doxytag: member="registers::pc_valid" ref="a87b4409ca50b4ccad122fad79a9d6665" args="reg[31:0]" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#a87b4409ca50b4ccad122fad79a9d6665">pc_valid</a></span> <b><span class="vhdlchar"> </span></b> <code> [reg[31:0]]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01734">1734</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<hr/>The documentation for this class was generated from the following file:<ul>
<li><a class="el" href="ao68000_8v_source.html">ao68000.v</a></li>
</ul>
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<hr class="footer"/><address class="footer"><small>Generated on Sat Jan 15 2011 16:54:37 for ao68000 by 
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.2 </small></address>
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