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<h1>Introduction </h1> </div>
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<p>The OpenCores <a class="el" href="classao68000.html" title="ao68000 top level module.">ao68000</a> IP Core is a Motorola MC68000 compatible processor.</p>
<h3>Features</h3>
<ul>
<li>CISC processor with microcode,</li>
<li>WISHBONE revision B.3 compatible MASTER interface,</li>
<li>Not cycle exact with the MC68000, some instructions take more cycles to complete, some less,</li>
<li>Uses about 4750 LE on Altera Cyclone II and about 45600 bits of RAM for microcode,</li>
<li>Tested against the WinUAE M68000 software emulator. Every 16-bit instruction was tested with random register contents and RAM contents (<a class="el" href="page_verification.html">Processor verification</a>). The result of execution was compared,</li>
<li>Contains a simple prefetch which is capable of holding up to 5 16-bit instruction words,</li>
<li>Documentation generated by Doxygen (www.doxygen.org) with doxverilog patch (<a href="http://developer.berlios.de/projects/doxverilog/">http://developer.berlios.de/projects/doxverilog/</a>). The specification is automatically extracted from the Doxygen HTML output.</li>
</ul>
<h3>WISHBONE compatibility</h3>
<ul>
<li>Version: WISHBONE specification Revision B.3,</li>
<li>General description: 32-bit WISHBONE Master interface,</li>
<li>WISHBONE signals described in <a class="el" href="page_spec_ports.html">IO Ports</a>,</li>
<li>Supported cycles: Master Read/Write, Master Block Read/Write, Master Read-Modify-Write for TAS instruction, Register Feedback Bus Cycles as described in chapter 4 of the WISHBONE specification,</li>
<li>Use of ERR_I: on memory access – bus error, on interrupt acknowledge: spurious interrupt,</li>
<li>Use of RTY_I: on memory access – repeat access, on interrupt acknowledge: generate auto-vector,</li>
<li>WISHBONE data port size: 32-bit,</li>
<li>Data port granularity: 8-bits,</li>
<li>Data port maximum operand size: 32-bits,</li>
<li>Data transfer ordering: BIG ENDIAN,</li>
<li>Data transfer sequencing: UNDEFINED,</li>
<li>Constraints on <code>CLK_I</code> signal: described in <a class="el" href="page_spec_clocks.html">Clocks</a>, maximum frequency: about 82 MHz.</li>
</ul>
<h3>Use</h3>
<ul>
<li>The <a class="el" href="classao68000.html" title="ao68000 top level module.">ao68000</a> is used as the processor for the OpenCores aoOCS project - Wishbone Amiga OCS SoC(<a href="http://opencores.org/project,aoocs">http://opencores.org/project,aoocs</a>).</li>
<li>It can also be used as a processor in a System-on-Chip booting Linux kernel version 2.6.33.1 up to <code>init</code> program lookup (<a class="el" href="page_soc_linux.html">System-on-Chip example with ao68000 running Linux</a>).</li>
</ul>
<h3>Similar projects</h3>
<p>Other free soft-core implementations of M68000 microprocessor include:</p>
<ul>
<li>OpenCores TG68 (<a href="http://www.opencores.org/project,tg68">http://www.opencores.org/project,tg68</a>) - runs Amiga software, used as part of the Minimig Core,</li>
<li>Suska Atari VHDL WF_68K00_IP Core (<a href="http://www.experiment-s.de/en">http://www.experiment-s.de/en</a>) - runs Atari software,</li>
<li>OpenCores K68 (<a href="http://www.opencores.org/project,k68">http://www.opencores.org/project,k68</a>) - no user and supervisor modes distinction, executes most instructions, but not all.</li>
<li>OpenCores ae68 (<a href="http://www.opencores.org/project,ae68">http://www.opencores.org/project,ae68</a>) - no files uploaded as of 27.03.2010.</li>
</ul>
<h3>Limitations</h3>
<ul>
<li>Microcode not optimized: some instructions take more cycles to execute than the original MC68000,</li>
<li>TRACE not tested,</li>
<li>The core is still large compared to other implementations.</li>
</ul>
<h3>TODO</h3>
<ul>
<li>Optimize the desgin and microcode,</li>
<li>Count the exact cycle count for every instruction,</li>
<li>Test TRACE,</li>
<li>Write more documentation.</li>
</ul>
<h3>Status</h3>
<ul>
<li>April 2010: Tested with WinUAE software MC68000 emulator,</li>
<li>April 2010: Booted Linux kernel up to <code>init</code> process lookup,</li>
<li>December 2010: Runs as a processor in OpenCores aoOCS project,</li>
<li>January 2011: Core area optimization by over 33% (Thanks to Frederic Requin).</li>
</ul>
<h3>Requirements</h3>
<ul>
<li>Icarus Verilog simulator (<a href="http://www.icarus.com/eda/verilog/">http://www.icarus.com/eda/verilog/</a>) is required to compile the <code>tb_ao68000</code> testbench/wrapper,</li>
<li>Access to Altera Quartus II instalation directory (directory eda/sim_lib/) is required to compile the <code>tb_ao68000</code> testbench/wrapper,</li>
<li>GCC (<a href="http://gcc.gnu.org">http://gcc.gnu.org</a>) is required to compile the WinUAE MC68000 software emulator,</li>
<li>Java runtime (<a href="http://java.sun.com">http://java.sun.com</a>) is required to run the <code>ao68000_tool</code> (<a class="el" href="page_tool.html">ao68000_tool documentation</a>),</li>
<li>Java SDK (<a href="http://java.sun.com">http://java.sun.com</a>) is required to compile the <code>ao68000_tool</code> (<a class="el" href="page_tool.html">ao68000_tool documentation</a>),</li>
<li>Altera Quartus II synthesis tool (<a href="http://www.altera.com">http://www.altera.com</a>) is required to synthesise the <code>soc_for_linux</code> System-on-Chip (<a class="el" href="page_soc_linux.html">System-on-Chip example with ao68000 running Linux</a>).</li>
</ul>
<h3>Glossary</h3>
<ul>
<li><b><a class="el" href="classao68000.html" title="ao68000 top level module.">ao68000</a></b> - the <a class="el" href="classao68000.html" title="ao68000 top level module.">ao68000</a> IP Core processor,</li>
<li><b>MC68000</b> - the original Motorola MC68000 processor. </li>
</ul>
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