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<h1>bus_syscon Module Reference</h1> </div>
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<p><p>WISHBONE priority and round-robin SYSCON. </p>
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<tr><td colspan="2"><h2><a name="Always Constructs"></a>
Always Constructs</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#abc43b26eff148b4ca2bcd513416d94b9">ALWAYS_33</a> </td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classbus__syscon.html#ab964ec62960befb50a2436bfc7c0f1d6">CLK_I</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classbus__syscon.html#ac31048a81c15f1feb37fad85968c8aeb">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
<tr><td colspan="2"><h2><a name="Inputs"></a>
Inputs</h2></td></tr>
<tr><td colspan="2"><div class="groupHeader">Clock and reset</div></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#ab964ec62960befb50a2436bfc7c0f1d6">CLK_I</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#ac31048a81c15f1feb37fad85968c8aeb">reset_n</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a6cb13040bd30068dc2042c13ed621689">halt_switch</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td colspan="2"><div class="groupHeader">Priority WISHBONE master interfaces</div></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a9fe8344030a265e105bca116642e4f16">masterP_dat_o</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td colspan="2"><div class="groupHeader">Round-robin WISHBONE master interfaces</div></td></tr>
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<tr><td colspan="2"><div class="groupHeader">AND/OR master address mask signals</div></td></tr>
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<tr><td colspan="2"><div class="groupHeader">WISHBONE slave interfaces</div></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#ae8dc7253e4fff8d1abe12d34ac191803">slave3_ack_o</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a542f7969a65a3a9a9ea52d6b36ec6bbb">slave3_rty_o</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a621f6b9a937ac5a9a74a42903b51dd57">slave3_dat_o</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a195c492ef0acdc0601a9e9ef756630b0">slave4_selected</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a9aef76d767064a2d6c680622842bfe82">slave4_ack_o</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a24b3a6599f97d11c6b3de4af097fab21">slave4_rty_o</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a27154c6d297ad7362c3685f8c3c2c0e9">slave4_err_o</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a405c2ef7023d0ab035e4b6055bbde950">slave4_dat_o</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#ab60801deafd7b7f33fbbfde7a9e741d6">slave5_ack_o</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a39b100ecae4171a6f212ef9d933e2d5f">slave5_rty_o</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a32aa24289b7c44cb88038ba3d93b5abb">slave7_rty_o</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a4a801eeff1c6f96035a872fc8efdfcdf">slave7_err_o</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#acbfe5025a0ddf90d7ca9714f84927cb7">slave7_dat_o</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a0f020b9776ff51e66cf86b963fc415f7">slave8_selected</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#aed1046a40945768c8d45f62a24c9ed47">slave8_ack_o</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a27d00f22badadd34aceb9622164e4781">slave8_rty_o</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a084aec23fc84531dec6d51ef859477e2">slave8_err_o</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a6ceb4d4f0c587250d01040cdd1254681">slave9_selected</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#afbb7633bbbeba1f82d8fd30e18ff2524">slave9_err_o</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a287d01a9efb78fe9c46648d7255bc1ca">slave10_selected</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#affa0290ff18f1d2161877b94f1acbc82">slave10_ack_o</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#aa2397c1d5ed0b9a1c60683130ebe2cef">slave10_rty_o</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#afb60f7ea4eb65743a5f827edcf834ce0">slave10_err_o</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a78d14b60b06e00903a792ad1d77ff497">slave11_selected</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#abb7bd3ab0c61b072f8e9ffd134ffe8d2">slave11_ack_o</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a9cf033bee86affc16fb9e2b610795c65">slave11_rty_o</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#ac9354d61c84294997c4594b5111600b0">slave11_err_o</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#ab894d866c396d562c9b78ffac9eef3f9">slave11_dat_o</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a3e1451a0c82e45ca9fc968ee359f5d1e">slave12_selected</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a15fa0aefc995ccf2c646718165ac3dfe">slave12_ack_o</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#adfc3860ba44fedb9d3090930782dc369">slave12_rty_o</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#ab79f0b97989c262b0a8611d8dd8c56b1">slave12_err_o</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a37ae46fb6b63a067254daf3ee3c30e6c">slave12_dat_o</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a9ede6b88ecf28671c42d2cac19a615ce">slave13_selected</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a4d9a4b357e514701727790e2a2852a13">slave13_ack_o</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a74dfbb0e1221aaddb9886cda027594b2">slave13_rty_o</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a0a1324bfbda7bfcdc87e5fb1ffacf852">slave13_err_o</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#adda20e6b873bffb6ad907fbae1c82861">slave13_dat_o</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#ac7d6549b17e6b3fd88f5d30d1829788b">slave14_selected</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#ae385e3020186e2bba2b623499dfeee74">slave14_ack_o</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#aa056b5891459a5833a300006fe28635b">slave14_rty_o</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#ae7a6494382912bda957d8c6aee681ccb">slave14_err_o</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a41cfcc25a59e3f3190cf2edb9444ee48">slave14_dat_o</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a1e490ab87c8a474cf171828de8d104e2">slave15_selected</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a2d91fbf38458701a03ccc89ec6aaf9e7">slave15_ack_o</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a7a482ec8b3e015ef00659e3557bf19df">slave15_rty_o</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a284bad867d4e58188b2aa72441bd9334">slave15_err_o</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#ad02d85c84ccfddd7e7488e8a0b009388">slave15_dat_o</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td colspan="2"><h2><a name="Outputs"></a>
Outputs</h2></td></tr>
<tr><td colspan="2"><div class="groupHeader">Priority WISHBONE master interfaces</div></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#ada506dcc258af5c5536f61ae5e633084">masterP_ack_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a5fc82c14fd55100279c5ca0050bc8a59">masterP_rty_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#ade3b05becb56a27afe1083b66ad946f8">masterP_err_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td colspan="2"><div class="groupHeader">Round-robin WISHBONE master interfaces</div></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#ad165278c58f53f4c13cabfe8866d0219">masterR1_ack_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#ae6e65b3bc10070d8fadefe1543d55868">masterR1_rty_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#adf9b5a612d72dac2388bc9321abdf774">masterR1_err_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a05ebe17bf774ac72f75347cfa90e21b9">masterR2_ack_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a6b482d52550863286351b36b711de2a3">masterR2_rty_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a0549875600cec709d926e39fdc85f166">masterR2_err_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a8fa4624686a34ab22a3c0d2477d6463c">masterR3_ack_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a8ada340451f11771c88e2ec91a727fe0">masterR3_rty_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#ac4cda8e2447a5ee9caf76ad82f7eefa1">masterR3_err_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a2d495bda95594bbd8818e4a6b38a717f">masterR4_ack_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a4e83a1294918d86f3fd1c69330b76de3">masterR4_rty_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a5182ba1a44a7cba8a1bc121115de4363">masterR4_err_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a685030f99a9395033b2405b223e1a035">masterR5_ack_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#af6026b1f0e925ec592ce32159e1e2b77">masterR5_rty_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#afe1b1e028487b7e49e725203d8f08d47">masterR5_err_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#acd30cafccb825f8667dc9f0c686b8529">masterR6_ack_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a2e8c7cd15a41ebe1216558c4c573d361">masterR6_rty_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a51384617dde95249b2ade033666727be">masterR6_err_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a15916f5472563b1e94cc3d4c10ec24c5">masterR7_ack_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a3bc28491729727ccd513d38180978459">masterR7_rty_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a665936d772b739839fc86c851cc57ff3">masterR7_err_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td colspan="2"><div class="groupHeader">Common WISHBONE master signals</div></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a24530aa819f3a233fb3f92ca6a6965a4">master_adr_o</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">2</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#ad2b3373f6394282e96e56fc1a6096a0d">master_we_o</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a3e2b0e0a8bb59d1182d3cf2d38592b1a">master_sel_o</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#ab7b5b6662a2b455d564d34ceae63be19">master_dat_o</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a56d4ab699ac3bf446b583f3aa68e296a">slave_dat_o</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td colspan="2"><div class="groupHeader">AND/OR master address mask signals</div></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#abc5fa49b136bcc55be39a2e29f01e263">master_adr_early_o</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">2</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td colspan="2"><div class="groupHeader">WISHBONE slave interfaces</div></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#abb9f512c20a336063e1ae191e7f5ad65">slave0_cyc_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a0014b1da93e8a757cc5faab834ed7e78">slave0_stb_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#ad3d33335ced6d9ae458bacf104a06aa8">slave1_cyc_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#ad0ec77685b6239d320abe765f6a49b5c">slave1_stb_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a2143b1fd92765def6b28ca72b8f3ce11">slave2_cyc_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a7fd5918d1b6578c1e6657c1279a20c55">slave2_stb_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a9520c9f4e9ddb8de1edf5b1c33e3bfce">slave3_cyc_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a70db2e44f130cee0697ab5fa40ea44b8">slave3_stb_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a0781af256941668f3221fef4590bc7ac">slave4_cyc_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a5cae87ec621a286e7f7e2fc5c02e2c1a">slave4_stb_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#ad4251578f47217bf05af5e2cbcbb4ed2">slave5_cyc_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#aaf084ce3dbd6e46dfa0b5096bb38729b">slave5_stb_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#ac7e6b38df5498247d7fb2331a047a969">slave6_cyc_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a65fdc0aad23dd8d2d535721b72bdabc5">slave6_stb_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#ab3e43099b79ff5eae40e3bf97eb0b1fb">slave7_cyc_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#ab26afd06e692c9e6fb856700009b152f">slave7_stb_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#ae9f79d9b0316cccc84831e4d2fa14b9e">slave8_cyc_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#afe4830f4ed051c82a3b156f764124c04">slave8_stb_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a9fc98d5a8298bcfae3cfaecc60de37c7">slave9_cyc_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#ad8795de1edce0f6eebd93d88d3a92e00">slave9_stb_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#aa89dca9a069546ad0ee6591c21d91939">slave10_cyc_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a992d5ff90f3c150f222b715074029145">slave10_stb_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a0a29a1147b1d162fe08e1497bade580b">slave11_cyc_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#aaada4f622c3960ea0f0093ce8d848d78">slave11_stb_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#afe8f4ceaf9e05ef16d37d4f826e0cdab">slave12_cyc_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#ac9024a113ab36feed7db0780db30bea0">slave12_stb_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a1d30c53ac1492a399d5bdcea1f4f9e97">slave13_cyc_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a4119edd92ed4bb1094978d07211d8a7e">slave13_stb_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a31f39d555a7cfb0b361993ec13c3fd44">slave14_cyc_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#aa4c036879984d2fc8d7b0dbe4c9342e9">slave14_stb_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#a53dc2da305fb7ab39b9818828071aea0">slave15_cyc_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#ad30a385cac2f1d80e01a121cb44f21a8">slave15_stb_i</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td colspan="2"><div class="groupHeader">Debug signals</div></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__syscon.html#aff069d1a7ae0371a0399bddf16d12abe">debug_syscon</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">7</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td colspan="2"><h2><a name="Signals"></a>
Signals</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classbus__syscon.html#a9eb95d18c5053aab98fa0660e06d80cc">master_cyc_stb_o</a> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classbus__syscon.html#a637fb5d32d290c5e04b4b6c1144caaa8">slave0_selected</a> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classbus__syscon.html#a14f9b22c806a4c54dff9a30bec68388b">master_ack_i</a> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classbus__syscon.html#a5b8736c002bf69e8ddd80782643b650e">master_rty_i</a> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classbus__syscon.html#abdcb59d4119f1071d644221a16e0db35">master_err_i</a> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar">[</span><span class="vhdldigit">4</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classbus__syscon.html#a32e1a6ae3e2bf599f8a83c1241422eb3">last_master</a> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">4</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classbus__syscon.html#a1b655884a9784b2977272cc44dc8da80">last_master_reg</a> </td></tr>
</table>
<hr/><a name="_details"></a><h2>Detailed Description</h2>
<p>WISHBONE priority and round-robin SYSCON. </p>
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00031">31</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
<hr/><h2>Member Function Documentation</h2>
<a class="anchor" id="abc43b26eff148b4ca2bcd513416d94b9"></a><!-- doxytag: member="bus_syscon::ALWAYS_33" ref="abc43b26eff148b4ca2bcd513416d94b9" args="CLK_I, reset_n" -->
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<td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_33 <td></td>
<td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classbus__syscon.html#ab964ec62960befb50a2436bfc7c0f1d6">CLK_I</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> , </td>
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<td class="paramkey"></td>
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<td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classbus__syscon.html#ac31048a81c15f1feb37fad85968c8aeb">reset_n</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> ) </td>
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<code> [Always Construct]</code></td>
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</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00602">602</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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</div>
<hr/><h2>Member Data Documentation</h2>
<a class="anchor" id="ab964ec62960befb50a2436bfc7c0f1d6"></a><!-- doxytag: member="bus_syscon::CLK_I" ref="ab964ec62960befb50a2436bfc7c0f1d6" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ab964ec62960befb50a2436bfc7c0f1d6">CLK_I</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00034">34</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="ac31048a81c15f1feb37fad85968c8aeb"></a><!-- doxytag: member="bus_syscon::reset_n" ref="ac31048a81c15f1feb37fad85968c8aeb" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ac31048a81c15f1feb37fad85968c8aeb">reset_n</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00035">35</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a6cb13040bd30068dc2042c13ed621689"></a><!-- doxytag: member="bus_syscon::halt_switch" ref="a6cb13040bd30068dc2042c13ed621689" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a6cb13040bd30068dc2042c13ed621689">halt_switch</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00036">36</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a31977e7b784c48f3c222600283556d45"></a><!-- doxytag: member="bus_syscon::masterP_cyc_o" ref="a31977e7b784c48f3c222600283556d45" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a31977e7b784c48f3c222600283556d45">masterP_cyc_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00041">41</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="ac7dbbba13adef5a5dd7801c052992269"></a><!-- doxytag: member="bus_syscon::masterP_stb_o" ref="ac7dbbba13adef5a5dd7801c052992269" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ac7dbbba13adef5a5dd7801c052992269">masterP_stb_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00042">42</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="ae7cd7b6d9e90dc30fd5324364fab9469"></a><!-- doxytag: member="bus_syscon::masterP_we_o" ref="ae7cd7b6d9e90dc30fd5324364fab9469" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ae7cd7b6d9e90dc30fd5324364fab9469">masterP_we_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00043">43</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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</div>
<a class="anchor" id="afc730100ae0832fdb84453cb1196e21b"></a><!-- doxytag: member="bus_syscon::masterP_adr_o" ref="afc730100ae0832fdb84453cb1196e21b" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#afc730100ae0832fdb84453cb1196e21b">masterP_adr_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">2</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00044">44</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="aae0907dbeb1a5750852ee23b0674d0f3"></a><!-- doxytag: member="bus_syscon::masterP_sel_o" ref="aae0907dbeb1a5750852ee23b0674d0f3" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#aae0907dbeb1a5750852ee23b0674d0f3">masterP_sel_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00045">45</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a9fe8344030a265e105bca116642e4f16"></a><!-- doxytag: member="bus_syscon::masterP_dat_o" ref="a9fe8344030a265e105bca116642e4f16" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a9fe8344030a265e105bca116642e4f16">masterP_dat_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00046">46</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="ada506dcc258af5c5536f61ae5e633084"></a><!-- doxytag: member="bus_syscon::masterP_ack_i" ref="ada506dcc258af5c5536f61ae5e633084" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ada506dcc258af5c5536f61ae5e633084">masterP_ack_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00047">47</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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</div>
<a class="anchor" id="a5fc82c14fd55100279c5ca0050bc8a59"></a><!-- doxytag: member="bus_syscon::masterP_rty_i" ref="a5fc82c14fd55100279c5ca0050bc8a59" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a5fc82c14fd55100279c5ca0050bc8a59">masterP_rty_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00048">48</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="ade3b05becb56a27afe1083b66ad946f8"></a><!-- doxytag: member="bus_syscon::masterP_err_i" ref="ade3b05becb56a27afe1083b66ad946f8" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ade3b05becb56a27afe1083b66ad946f8">masterP_err_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00049">49</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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</div>
<a class="anchor" id="a87fbc356b4a8cb1a3bce32ac3e2b232f"></a><!-- doxytag: member="bus_syscon::masterR1_cyc_o" ref="a87fbc356b4a8cb1a3bce32ac3e2b232f" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a87fbc356b4a8cb1a3bce32ac3e2b232f">masterR1_cyc_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00054">54</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a885750b449b61b25bc17217eb5a3612c"></a><!-- doxytag: member="bus_syscon::masterR1_stb_o" ref="a885750b449b61b25bc17217eb5a3612c" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a885750b449b61b25bc17217eb5a3612c">masterR1_stb_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00055">55</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a5a23fc0ea2a147b82078a28dc5b84b25"></a><!-- doxytag: member="bus_syscon::masterR1_we_o" ref="a5a23fc0ea2a147b82078a28dc5b84b25" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a5a23fc0ea2a147b82078a28dc5b84b25">masterR1_we_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00056">56</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="ac33c887f71e9ef590ecf051aa9072ebc"></a><!-- doxytag: member="bus_syscon::masterR1_adr_o" ref="ac33c887f71e9ef590ecf051aa9072ebc" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ac33c887f71e9ef590ecf051aa9072ebc">masterR1_adr_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">2</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00057">57</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="ae95f05d38beefb01406e2e96acfab983"></a><!-- doxytag: member="bus_syscon::masterR1_sel_o" ref="ae95f05d38beefb01406e2e96acfab983" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ae95f05d38beefb01406e2e96acfab983">masterR1_sel_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00058">58</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a4f93f8b395ecbd62ff30d4752f603fdb"></a><!-- doxytag: member="bus_syscon::masterR1_dat_o" ref="a4f93f8b395ecbd62ff30d4752f603fdb" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a4f93f8b395ecbd62ff30d4752f603fdb">masterR1_dat_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00059">59</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="ad165278c58f53f4c13cabfe8866d0219"></a><!-- doxytag: member="bus_syscon::masterR1_ack_i" ref="ad165278c58f53f4c13cabfe8866d0219" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ad165278c58f53f4c13cabfe8866d0219">masterR1_ack_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00060">60</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="ae6e65b3bc10070d8fadefe1543d55868"></a><!-- doxytag: member="bus_syscon::masterR1_rty_i" ref="ae6e65b3bc10070d8fadefe1543d55868" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ae6e65b3bc10070d8fadefe1543d55868">masterR1_rty_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00061">61</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="adf9b5a612d72dac2388bc9321abdf774"></a><!-- doxytag: member="bus_syscon::masterR1_err_i" ref="adf9b5a612d72dac2388bc9321abdf774" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#adf9b5a612d72dac2388bc9321abdf774">masterR1_err_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00062">62</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a89945c032748f60ee906bc4964e75f2d"></a><!-- doxytag: member="bus_syscon::masterR2_cyc_o" ref="a89945c032748f60ee906bc4964e75f2d" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a89945c032748f60ee906bc4964e75f2d">masterR2_cyc_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00064">64</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a5f541d5bf2d8957aa3df2c44b9575872"></a><!-- doxytag: member="bus_syscon::masterR2_stb_o" ref="a5f541d5bf2d8957aa3df2c44b9575872" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a5f541d5bf2d8957aa3df2c44b9575872">masterR2_stb_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00065">65</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a12610cc20bff188a4a2e7fdcc981235a"></a><!-- doxytag: member="bus_syscon::masterR2_we_o" ref="a12610cc20bff188a4a2e7fdcc981235a" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a12610cc20bff188a4a2e7fdcc981235a">masterR2_we_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00066">66</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="af5491bfc76f34049ce20d7e322c30440"></a><!-- doxytag: member="bus_syscon::masterR2_adr_o" ref="af5491bfc76f34049ce20d7e322c30440" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#af5491bfc76f34049ce20d7e322c30440">masterR2_adr_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">2</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00067">67</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a3642ec770851154518f99f4662ba1dbd"></a><!-- doxytag: member="bus_syscon::masterR2_sel_o" ref="a3642ec770851154518f99f4662ba1dbd" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a3642ec770851154518f99f4662ba1dbd">masterR2_sel_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00068">68</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="ad51bd1c6a5ef0f2a98b36352bdbb08b2"></a><!-- doxytag: member="bus_syscon::masterR2_dat_o" ref="ad51bd1c6a5ef0f2a98b36352bdbb08b2" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ad51bd1c6a5ef0f2a98b36352bdbb08b2">masterR2_dat_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00069">69</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a05ebe17bf774ac72f75347cfa90e21b9"></a><!-- doxytag: member="bus_syscon::masterR2_ack_i" ref="a05ebe17bf774ac72f75347cfa90e21b9" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a05ebe17bf774ac72f75347cfa90e21b9">masterR2_ack_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00070">70</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a6b482d52550863286351b36b711de2a3"></a><!-- doxytag: member="bus_syscon::masterR2_rty_i" ref="a6b482d52550863286351b36b711de2a3" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a6b482d52550863286351b36b711de2a3">masterR2_rty_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00071">71</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a0549875600cec709d926e39fdc85f166"></a><!-- doxytag: member="bus_syscon::masterR2_err_i" ref="a0549875600cec709d926e39fdc85f166" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a0549875600cec709d926e39fdc85f166">masterR2_err_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00072">72</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a01c0e1d0cd23fd2b76d6b034e347bc4e"></a><!-- doxytag: member="bus_syscon::masterR3_cyc_o" ref="a01c0e1d0cd23fd2b76d6b034e347bc4e" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a01c0e1d0cd23fd2b76d6b034e347bc4e">masterR3_cyc_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00074">74</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a0805e179d4c7231e78752520700c274f"></a><!-- doxytag: member="bus_syscon::masterR3_stb_o" ref="a0805e179d4c7231e78752520700c274f" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a0805e179d4c7231e78752520700c274f">masterR3_stb_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00075">75</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a43bd772f7aa006cd035cde1c61544a36"></a><!-- doxytag: member="bus_syscon::masterR3_we_o" ref="a43bd772f7aa006cd035cde1c61544a36" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a43bd772f7aa006cd035cde1c61544a36">masterR3_we_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00076">76</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a60c1c2c609116b428834e401bbf83e97"></a><!-- doxytag: member="bus_syscon::masterR3_adr_o" ref="a60c1c2c609116b428834e401bbf83e97" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a60c1c2c609116b428834e401bbf83e97">masterR3_adr_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">2</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00077">77</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a1affc23c7bbad9fcad7be929a8d55060"></a><!-- doxytag: member="bus_syscon::masterR3_sel_o" ref="a1affc23c7bbad9fcad7be929a8d55060" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a1affc23c7bbad9fcad7be929a8d55060">masterR3_sel_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00078">78</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a80c9d5bf618d5b0d11c347694b5bae71"></a><!-- doxytag: member="bus_syscon::masterR3_dat_o" ref="a80c9d5bf618d5b0d11c347694b5bae71" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a80c9d5bf618d5b0d11c347694b5bae71">masterR3_dat_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00079">79</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a8fa4624686a34ab22a3c0d2477d6463c"></a><!-- doxytag: member="bus_syscon::masterR3_ack_i" ref="a8fa4624686a34ab22a3c0d2477d6463c" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a8fa4624686a34ab22a3c0d2477d6463c">masterR3_ack_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00080">80</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a8ada340451f11771c88e2ec91a727fe0"></a><!-- doxytag: member="bus_syscon::masterR3_rty_i" ref="a8ada340451f11771c88e2ec91a727fe0" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a8ada340451f11771c88e2ec91a727fe0">masterR3_rty_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00081">81</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="ac4cda8e2447a5ee9caf76ad82f7eefa1"></a><!-- doxytag: member="bus_syscon::masterR3_err_i" ref="ac4cda8e2447a5ee9caf76ad82f7eefa1" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ac4cda8e2447a5ee9caf76ad82f7eefa1">masterR3_err_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00082">82</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="aad1b8359a0b42d7d62ebde2c2f2b6796"></a><!-- doxytag: member="bus_syscon::masterR4_cyc_o" ref="aad1b8359a0b42d7d62ebde2c2f2b6796" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#aad1b8359a0b42d7d62ebde2c2f2b6796">masterR4_cyc_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00084">84</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a5377b5299c7cf653326290c3c4a908b2"></a><!-- doxytag: member="bus_syscon::masterR4_stb_o" ref="a5377b5299c7cf653326290c3c4a908b2" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a5377b5299c7cf653326290c3c4a908b2">masterR4_stb_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00085">85</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="ad13765e95ea015a738e80c1c2907afb0"></a><!-- doxytag: member="bus_syscon::masterR4_we_o" ref="ad13765e95ea015a738e80c1c2907afb0" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ad13765e95ea015a738e80c1c2907afb0">masterR4_we_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00086">86</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a6589b5d347420b045b824a997fd80efe"></a><!-- doxytag: member="bus_syscon::masterR4_adr_o" ref="a6589b5d347420b045b824a997fd80efe" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a6589b5d347420b045b824a997fd80efe">masterR4_adr_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">2</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00087">87</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a0f889c7df47ebeb7c98e966a1b08d148"></a><!-- doxytag: member="bus_syscon::masterR4_sel_o" ref="a0f889c7df47ebeb7c98e966a1b08d148" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a0f889c7df47ebeb7c98e966a1b08d148">masterR4_sel_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00088">88</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a370c3cb9eae4091efdb03a38c7f6147f"></a><!-- doxytag: member="bus_syscon::masterR4_dat_o" ref="a370c3cb9eae4091efdb03a38c7f6147f" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a370c3cb9eae4091efdb03a38c7f6147f">masterR4_dat_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00089">89</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a2d495bda95594bbd8818e4a6b38a717f"></a><!-- doxytag: member="bus_syscon::masterR4_ack_i" ref="a2d495bda95594bbd8818e4a6b38a717f" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a2d495bda95594bbd8818e4a6b38a717f">masterR4_ack_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00090">90</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a4e83a1294918d86f3fd1c69330b76de3"></a><!-- doxytag: member="bus_syscon::masterR4_rty_i" ref="a4e83a1294918d86f3fd1c69330b76de3" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a4e83a1294918d86f3fd1c69330b76de3">masterR4_rty_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00091">91</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a5182ba1a44a7cba8a1bc121115de4363"></a><!-- doxytag: member="bus_syscon::masterR4_err_i" ref="a5182ba1a44a7cba8a1bc121115de4363" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a5182ba1a44a7cba8a1bc121115de4363">masterR4_err_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00092">92</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="aa2d23e5a67888b3d304eab3e75f56d65"></a><!-- doxytag: member="bus_syscon::masterR5_cyc_o" ref="aa2d23e5a67888b3d304eab3e75f56d65" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#aa2d23e5a67888b3d304eab3e75f56d65">masterR5_cyc_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00094">94</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a075d22dc885f745c85aec16eb24ff740"></a><!-- doxytag: member="bus_syscon::masterR5_stb_o" ref="a075d22dc885f745c85aec16eb24ff740" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a075d22dc885f745c85aec16eb24ff740">masterR5_stb_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00095">95</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a5508521aa5f4b17160a8a9bf64a8cb31"></a><!-- doxytag: member="bus_syscon::masterR5_we_o" ref="a5508521aa5f4b17160a8a9bf64a8cb31" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a5508521aa5f4b17160a8a9bf64a8cb31">masterR5_we_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00096">96</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="abde16163bf7494bf575f67d22215c100"></a><!-- doxytag: member="bus_syscon::masterR5_adr_o" ref="abde16163bf7494bf575f67d22215c100" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#abde16163bf7494bf575f67d22215c100">masterR5_adr_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">2</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00097">97</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="ae20b6fc51241d21fa4f3de2716fa72aa"></a><!-- doxytag: member="bus_syscon::masterR5_sel_o" ref="ae20b6fc51241d21fa4f3de2716fa72aa" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ae20b6fc51241d21fa4f3de2716fa72aa">masterR5_sel_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00098">98</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a92beca25fc3089e53f68c5694e6710ca"></a><!-- doxytag: member="bus_syscon::masterR5_dat_o" ref="a92beca25fc3089e53f68c5694e6710ca" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a92beca25fc3089e53f68c5694e6710ca">masterR5_dat_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00099">99</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a685030f99a9395033b2405b223e1a035"></a><!-- doxytag: member="bus_syscon::masterR5_ack_i" ref="a685030f99a9395033b2405b223e1a035" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a685030f99a9395033b2405b223e1a035">masterR5_ack_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00100">100</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="af6026b1f0e925ec592ce32159e1e2b77"></a><!-- doxytag: member="bus_syscon::masterR5_rty_i" ref="af6026b1f0e925ec592ce32159e1e2b77" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#af6026b1f0e925ec592ce32159e1e2b77">masterR5_rty_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00101">101</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="afe1b1e028487b7e49e725203d8f08d47"></a><!-- doxytag: member="bus_syscon::masterR5_err_i" ref="afe1b1e028487b7e49e725203d8f08d47" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#afe1b1e028487b7e49e725203d8f08d47">masterR5_err_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00102">102</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a8d92d8ee85c87cadac29602239902813"></a><!-- doxytag: member="bus_syscon::masterR6_cyc_o" ref="a8d92d8ee85c87cadac29602239902813" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a8d92d8ee85c87cadac29602239902813">masterR6_cyc_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00104">104</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="afb4f1816bace97a19ba26b87ca10b641"></a><!-- doxytag: member="bus_syscon::masterR6_stb_o" ref="afb4f1816bace97a19ba26b87ca10b641" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#afb4f1816bace97a19ba26b87ca10b641">masterR6_stb_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00105">105</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a348106fc81200cb8d2b19426127e1348"></a><!-- doxytag: member="bus_syscon::masterR6_we_o" ref="a348106fc81200cb8d2b19426127e1348" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a348106fc81200cb8d2b19426127e1348">masterR6_we_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00106">106</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="ac2e53ebddd0058de88596c1e9d332d01"></a><!-- doxytag: member="bus_syscon::masterR6_adr_o" ref="ac2e53ebddd0058de88596c1e9d332d01" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ac2e53ebddd0058de88596c1e9d332d01">masterR6_adr_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">2</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00107">107</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a4589ebf7448d09f1b94b7a11b026ac28"></a><!-- doxytag: member="bus_syscon::masterR6_sel_o" ref="a4589ebf7448d09f1b94b7a11b026ac28" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a4589ebf7448d09f1b94b7a11b026ac28">masterR6_sel_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00108">108</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="aa0c664010ab2469c4c54972b27e4ece3"></a><!-- doxytag: member="bus_syscon::masterR6_dat_o" ref="aa0c664010ab2469c4c54972b27e4ece3" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#aa0c664010ab2469c4c54972b27e4ece3">masterR6_dat_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00109">109</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="acd30cafccb825f8667dc9f0c686b8529"></a><!-- doxytag: member="bus_syscon::masterR6_ack_i" ref="acd30cafccb825f8667dc9f0c686b8529" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#acd30cafccb825f8667dc9f0c686b8529">masterR6_ack_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00110">110</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a2e8c7cd15a41ebe1216558c4c573d361"></a><!-- doxytag: member="bus_syscon::masterR6_rty_i" ref="a2e8c7cd15a41ebe1216558c4c573d361" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a2e8c7cd15a41ebe1216558c4c573d361">masterR6_rty_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00111">111</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a51384617dde95249b2ade033666727be"></a><!-- doxytag: member="bus_syscon::masterR6_err_i" ref="a51384617dde95249b2ade033666727be" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a51384617dde95249b2ade033666727be">masterR6_err_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00112">112</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a3f6af322a2940dc979b8ff72007579cc"></a><!-- doxytag: member="bus_syscon::masterR7_cyc_o" ref="a3f6af322a2940dc979b8ff72007579cc" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a3f6af322a2940dc979b8ff72007579cc">masterR7_cyc_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00114">114</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="ab8fef543d006e23917b72be3164d6092"></a><!-- doxytag: member="bus_syscon::masterR7_stb_o" ref="ab8fef543d006e23917b72be3164d6092" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ab8fef543d006e23917b72be3164d6092">masterR7_stb_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00115">115</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a2b0082c1fafd842878833350e65142c3"></a><!-- doxytag: member="bus_syscon::masterR7_we_o" ref="a2b0082c1fafd842878833350e65142c3" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a2b0082c1fafd842878833350e65142c3">masterR7_we_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00116">116</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a62d020c789c60713e7568433fa41dbe0"></a><!-- doxytag: member="bus_syscon::masterR7_adr_o" ref="a62d020c789c60713e7568433fa41dbe0" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a62d020c789c60713e7568433fa41dbe0">masterR7_adr_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">2</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00117">117</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="ab6ea1494c50b37d9df21398dd1c536f0"></a><!-- doxytag: member="bus_syscon::masterR7_sel_o" ref="ab6ea1494c50b37d9df21398dd1c536f0" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ab6ea1494c50b37d9df21398dd1c536f0">masterR7_sel_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00118">118</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="ad52ad2d119d45a14e5f0ea8ddb24bd21"></a><!-- doxytag: member="bus_syscon::masterR7_dat_o" ref="ad52ad2d119d45a14e5f0ea8ddb24bd21" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ad52ad2d119d45a14e5f0ea8ddb24bd21">masterR7_dat_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00119">119</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a15916f5472563b1e94cc3d4c10ec24c5"></a><!-- doxytag: member="bus_syscon::masterR7_ack_i" ref="a15916f5472563b1e94cc3d4c10ec24c5" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a15916f5472563b1e94cc3d4c10ec24c5">masterR7_ack_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00120">120</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a3bc28491729727ccd513d38180978459"></a><!-- doxytag: member="bus_syscon::masterR7_rty_i" ref="a3bc28491729727ccd513d38180978459" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a3bc28491729727ccd513d38180978459">masterR7_rty_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00121">121</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a665936d772b739839fc86c851cc57ff3"></a><!-- doxytag: member="bus_syscon::masterR7_err_i" ref="a665936d772b739839fc86c851cc57ff3" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a665936d772b739839fc86c851cc57ff3">masterR7_err_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00122">122</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a24530aa819f3a233fb3f92ca6a6965a4"></a><!-- doxytag: member="bus_syscon::master_adr_o" ref="a24530aa819f3a233fb3f92ca6a6965a4" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a24530aa819f3a233fb3f92ca6a6965a4">master_adr_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">2</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00127">127</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="ad2b3373f6394282e96e56fc1a6096a0d"></a><!-- doxytag: member="bus_syscon::master_we_o" ref="ad2b3373f6394282e96e56fc1a6096a0d" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ad2b3373f6394282e96e56fc1a6096a0d">master_we_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00128">128</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a3e2b0e0a8bb59d1182d3cf2d38592b1a"></a><!-- doxytag: member="bus_syscon::master_sel_o" ref="a3e2b0e0a8bb59d1182d3cf2d38592b1a" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a3e2b0e0a8bb59d1182d3cf2d38592b1a">master_sel_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00129">129</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="ab7b5b6662a2b455d564d34ceae63be19"></a><!-- doxytag: member="bus_syscon::master_dat_o" ref="ab7b5b6662a2b455d564d34ceae63be19" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ab7b5b6662a2b455d564d34ceae63be19">master_dat_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00130">130</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a56d4ab699ac3bf446b583f3aa68e296a"></a><!-- doxytag: member="bus_syscon::slave_dat_o" ref="a56d4ab699ac3bf446b583f3aa68e296a" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a56d4ab699ac3bf446b583f3aa68e296a">slave_dat_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00131">131</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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</div>
<a class="anchor" id="abc5fa49b136bcc55be39a2e29f01e263"></a><!-- doxytag: member="bus_syscon::master_adr_early_o" ref="abc5fa49b136bcc55be39a2e29f01e263" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#abc5fa49b136bcc55be39a2e29f01e263">master_adr_early_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">2</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00136">136</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="ae147397f076cbabba9c51894b37a1a5c"></a><!-- doxytag: member="bus_syscon::master_adr_and_mask" ref="ae147397f076cbabba9c51894b37a1a5c" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ae147397f076cbabba9c51894b37a1a5c">master_adr_and_mask</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">2</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00137">137</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a0f44be59c6f8db05e62258605d9e9f6c"></a><!-- doxytag: member="bus_syscon::master_adr_or_mask" ref="a0f44be59c6f8db05e62258605d9e9f6c" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a0f44be59c6f8db05e62258605d9e9f6c">master_adr_or_mask</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">2</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00138">138</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="abb9f512c20a336063e1ae191e7f5ad65"></a><!-- doxytag: member="bus_syscon::slave0_cyc_i" ref="abb9f512c20a336063e1ae191e7f5ad65" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#abb9f512c20a336063e1ae191e7f5ad65">slave0_cyc_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00143">143</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a0014b1da93e8a757cc5faab834ed7e78"></a><!-- doxytag: member="bus_syscon::slave0_stb_i" ref="a0014b1da93e8a757cc5faab834ed7e78" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a0014b1da93e8a757cc5faab834ed7e78">slave0_stb_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00144">144</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a8e7a434e52386112212eac9b3268772a"></a><!-- doxytag: member="bus_syscon::slave0_ack_o" ref="a8e7a434e52386112212eac9b3268772a" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a8e7a434e52386112212eac9b3268772a">slave0_ack_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00145">145</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a7eb7acc9c2a43b885aee69796724a0cc"></a><!-- doxytag: member="bus_syscon::slave0_rty_o" ref="a7eb7acc9c2a43b885aee69796724a0cc" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a7eb7acc9c2a43b885aee69796724a0cc">slave0_rty_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00146">146</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a3f436e87011936687de4b15a0fc470a9"></a><!-- doxytag: member="bus_syscon::slave0_err_o" ref="a3f436e87011936687de4b15a0fc470a9" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a3f436e87011936687de4b15a0fc470a9">slave0_err_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00147">147</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="ac018177ee72c96101ecfb61f91653f05"></a><!-- doxytag: member="bus_syscon::slave0_dat_o" ref="ac018177ee72c96101ecfb61f91653f05" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ac018177ee72c96101ecfb61f91653f05">slave0_dat_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00148">148</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a5956e9f9a40f46fd84ecdc41b4a0f459"></a><!-- doxytag: member="bus_syscon::slave1_selected" ref="a5956e9f9a40f46fd84ecdc41b4a0f459" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a5956e9f9a40f46fd84ecdc41b4a0f459">slave1_selected</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00150">150</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="ad3d33335ced6d9ae458bacf104a06aa8"></a><!-- doxytag: member="bus_syscon::slave1_cyc_i" ref="ad3d33335ced6d9ae458bacf104a06aa8" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ad3d33335ced6d9ae458bacf104a06aa8">slave1_cyc_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00151">151</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="ad0ec77685b6239d320abe765f6a49b5c"></a><!-- doxytag: member="bus_syscon::slave1_stb_i" ref="ad0ec77685b6239d320abe765f6a49b5c" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ad0ec77685b6239d320abe765f6a49b5c">slave1_stb_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00152">152</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a9fe7c95c9ce30146684494fe26c2e30e"></a><!-- doxytag: member="bus_syscon::slave1_ack_o" ref="a9fe7c95c9ce30146684494fe26c2e30e" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a9fe7c95c9ce30146684494fe26c2e30e">slave1_ack_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00153">153</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a18186e4c8d3bf652b6eef032f53ad618"></a><!-- doxytag: member="bus_syscon::slave1_rty_o" ref="a18186e4c8d3bf652b6eef032f53ad618" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a18186e4c8d3bf652b6eef032f53ad618">slave1_rty_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00154">154</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="aebf3cf19abdcd349e560031926602e1a"></a><!-- doxytag: member="bus_syscon::slave1_err_o" ref="aebf3cf19abdcd349e560031926602e1a" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#aebf3cf19abdcd349e560031926602e1a">slave1_err_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00155">155</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="ab38ef1a0018abb7616361afedf204eee"></a><!-- doxytag: member="bus_syscon::slave1_dat_o" ref="ab38ef1a0018abb7616361afedf204eee" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ab38ef1a0018abb7616361afedf204eee">slave1_dat_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00156">156</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a9665a7e00a754de45089d5f417770f6c"></a><!-- doxytag: member="bus_syscon::slave2_selected" ref="a9665a7e00a754de45089d5f417770f6c" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a9665a7e00a754de45089d5f417770f6c">slave2_selected</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00158">158</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a2143b1fd92765def6b28ca72b8f3ce11"></a><!-- doxytag: member="bus_syscon::slave2_cyc_i" ref="a2143b1fd92765def6b28ca72b8f3ce11" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a2143b1fd92765def6b28ca72b8f3ce11">slave2_cyc_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00159">159</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a7fd5918d1b6578c1e6657c1279a20c55"></a><!-- doxytag: member="bus_syscon::slave2_stb_i" ref="a7fd5918d1b6578c1e6657c1279a20c55" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a7fd5918d1b6578c1e6657c1279a20c55">slave2_stb_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00160">160</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="ac9246a3683b15412f736032d9b39c6d4"></a><!-- doxytag: member="bus_syscon::slave2_ack_o" ref="ac9246a3683b15412f736032d9b39c6d4" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ac9246a3683b15412f736032d9b39c6d4">slave2_ack_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00161">161</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="ac909a213c90447a313bfe50f77e8da2a"></a><!-- doxytag: member="bus_syscon::slave2_rty_o" ref="ac909a213c90447a313bfe50f77e8da2a" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ac909a213c90447a313bfe50f77e8da2a">slave2_rty_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00162">162</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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</div>
<a class="anchor" id="ad658a200e154abc0b9f79d0d3a035323"></a><!-- doxytag: member="bus_syscon::slave2_err_o" ref="ad658a200e154abc0b9f79d0d3a035323" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ad658a200e154abc0b9f79d0d3a035323">slave2_err_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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</table>
</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00163">163</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="aaee8ccec4821c4a8ba12c1ad1b54e0bb"></a><!-- doxytag: member="bus_syscon::slave2_dat_o" ref="aaee8ccec4821c4a8ba12c1ad1b54e0bb" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#aaee8ccec4821c4a8ba12c1ad1b54e0bb">slave2_dat_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00164">164</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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</div>
<a class="anchor" id="afbaec7e3615ab2aafdfd011e6684cf17"></a><!-- doxytag: member="bus_syscon::slave3_selected" ref="afbaec7e3615ab2aafdfd011e6684cf17" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#afbaec7e3615ab2aafdfd011e6684cf17">slave3_selected</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00166">166</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a9520c9f4e9ddb8de1edf5b1c33e3bfce"></a><!-- doxytag: member="bus_syscon::slave3_cyc_i" ref="a9520c9f4e9ddb8de1edf5b1c33e3bfce" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a9520c9f4e9ddb8de1edf5b1c33e3bfce">slave3_cyc_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00167">167</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a70db2e44f130cee0697ab5fa40ea44b8"></a><!-- doxytag: member="bus_syscon::slave3_stb_i" ref="a70db2e44f130cee0697ab5fa40ea44b8" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a70db2e44f130cee0697ab5fa40ea44b8">slave3_stb_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00168">168</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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</div>
<a class="anchor" id="ae8dc7253e4fff8d1abe12d34ac191803"></a><!-- doxytag: member="bus_syscon::slave3_ack_o" ref="ae8dc7253e4fff8d1abe12d34ac191803" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ae8dc7253e4fff8d1abe12d34ac191803">slave3_ack_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00169">169</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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</div>
<a class="anchor" id="a542f7969a65a3a9a9ea52d6b36ec6bbb"></a><!-- doxytag: member="bus_syscon::slave3_rty_o" ref="a542f7969a65a3a9a9ea52d6b36ec6bbb" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a542f7969a65a3a9a9ea52d6b36ec6bbb">slave3_rty_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00170">170</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="aab0d971df2612a4e94dc64e894b230bc"></a><!-- doxytag: member="bus_syscon::slave3_err_o" ref="aab0d971df2612a4e94dc64e894b230bc" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#aab0d971df2612a4e94dc64e894b230bc">slave3_err_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00171">171</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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</div>
<a class="anchor" id="a621f6b9a937ac5a9a74a42903b51dd57"></a><!-- doxytag: member="bus_syscon::slave3_dat_o" ref="a621f6b9a937ac5a9a74a42903b51dd57" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a621f6b9a937ac5a9a74a42903b51dd57">slave3_dat_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00172">172</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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</div>
<a class="anchor" id="a195c492ef0acdc0601a9e9ef756630b0"></a><!-- doxytag: member="bus_syscon::slave4_selected" ref="a195c492ef0acdc0601a9e9ef756630b0" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a195c492ef0acdc0601a9e9ef756630b0">slave4_selected</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00174">174</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a0781af256941668f3221fef4590bc7ac"></a><!-- doxytag: member="bus_syscon::slave4_cyc_i" ref="a0781af256941668f3221fef4590bc7ac" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a0781af256941668f3221fef4590bc7ac">slave4_cyc_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00175">175</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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</div>
<a class="anchor" id="a5cae87ec621a286e7f7e2fc5c02e2c1a"></a><!-- doxytag: member="bus_syscon::slave4_stb_i" ref="a5cae87ec621a286e7f7e2fc5c02e2c1a" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a5cae87ec621a286e7f7e2fc5c02e2c1a">slave4_stb_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00176">176</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a9aef76d767064a2d6c680622842bfe82"></a><!-- doxytag: member="bus_syscon::slave4_ack_o" ref="a9aef76d767064a2d6c680622842bfe82" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a9aef76d767064a2d6c680622842bfe82">slave4_ack_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00177">177</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a24b3a6599f97d11c6b3de4af097fab21"></a><!-- doxytag: member="bus_syscon::slave4_rty_o" ref="a24b3a6599f97d11c6b3de4af097fab21" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a24b3a6599f97d11c6b3de4af097fab21">slave4_rty_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00178">178</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a27154c6d297ad7362c3685f8c3c2c0e9"></a><!-- doxytag: member="bus_syscon::slave4_err_o" ref="a27154c6d297ad7362c3685f8c3c2c0e9" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a27154c6d297ad7362c3685f8c3c2c0e9">slave4_err_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00179">179</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a405c2ef7023d0ab035e4b6055bbde950"></a><!-- doxytag: member="bus_syscon::slave4_dat_o" ref="a405c2ef7023d0ab035e4b6055bbde950" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a405c2ef7023d0ab035e4b6055bbde950">slave4_dat_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00180">180</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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</div>
<a class="anchor" id="a3c37d39c4c72331ffd9fc6e1478416e3"></a><!-- doxytag: member="bus_syscon::slave5_selected" ref="a3c37d39c4c72331ffd9fc6e1478416e3" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a3c37d39c4c72331ffd9fc6e1478416e3">slave5_selected</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00182">182</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="ad4251578f47217bf05af5e2cbcbb4ed2"></a><!-- doxytag: member="bus_syscon::slave5_cyc_i" ref="ad4251578f47217bf05af5e2cbcbb4ed2" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ad4251578f47217bf05af5e2cbcbb4ed2">slave5_cyc_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00183">183</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="aaf084ce3dbd6e46dfa0b5096bb38729b"></a><!-- doxytag: member="bus_syscon::slave5_stb_i" ref="aaf084ce3dbd6e46dfa0b5096bb38729b" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#aaf084ce3dbd6e46dfa0b5096bb38729b">slave5_stb_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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</table>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00184">184</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="ab60801deafd7b7f33fbbfde7a9e741d6"></a><!-- doxytag: member="bus_syscon::slave5_ack_o" ref="ab60801deafd7b7f33fbbfde7a9e741d6" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ab60801deafd7b7f33fbbfde7a9e741d6">slave5_ack_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00185">185</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a39b100ecae4171a6f212ef9d933e2d5f"></a><!-- doxytag: member="bus_syscon::slave5_rty_o" ref="a39b100ecae4171a6f212ef9d933e2d5f" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a39b100ecae4171a6f212ef9d933e2d5f">slave5_rty_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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</table>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00186">186</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a811bb01be14cdcaecc33154bd5d65066"></a><!-- doxytag: member="bus_syscon::slave5_err_o" ref="a811bb01be14cdcaecc33154bd5d65066" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a811bb01be14cdcaecc33154bd5d65066">slave5_err_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00187">187</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a12e543729491303e6c100e299cb5a968"></a><!-- doxytag: member="bus_syscon::slave5_dat_o" ref="a12e543729491303e6c100e299cb5a968" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a12e543729491303e6c100e299cb5a968">slave5_dat_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00188">188</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="ae4a5cfa29fa7ffbe038b191777e54b99"></a><!-- doxytag: member="bus_syscon::slave6_selected" ref="ae4a5cfa29fa7ffbe038b191777e54b99" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ae4a5cfa29fa7ffbe038b191777e54b99">slave6_selected</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00190">190</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="ac7e6b38df5498247d7fb2331a047a969"></a><!-- doxytag: member="bus_syscon::slave6_cyc_i" ref="ac7e6b38df5498247d7fb2331a047a969" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ac7e6b38df5498247d7fb2331a047a969">slave6_cyc_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00191">191</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a65fdc0aad23dd8d2d535721b72bdabc5"></a><!-- doxytag: member="bus_syscon::slave6_stb_i" ref="a65fdc0aad23dd8d2d535721b72bdabc5" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a65fdc0aad23dd8d2d535721b72bdabc5">slave6_stb_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00192">192</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a0748525eaeda81fc8cebedf1574fe49e"></a><!-- doxytag: member="bus_syscon::slave6_ack_o" ref="a0748525eaeda81fc8cebedf1574fe49e" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a0748525eaeda81fc8cebedf1574fe49e">slave6_ack_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00193">193</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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</div>
<a class="anchor" id="a1e7ea6246a5ae9ee5da1504e45663dcb"></a><!-- doxytag: member="bus_syscon::slave6_rty_o" ref="a1e7ea6246a5ae9ee5da1504e45663dcb" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a1e7ea6246a5ae9ee5da1504e45663dcb">slave6_rty_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00194">194</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="ab4ba9483c0417dc9035eae39d93a1947"></a><!-- doxytag: member="bus_syscon::slave6_err_o" ref="ab4ba9483c0417dc9035eae39d93a1947" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ab4ba9483c0417dc9035eae39d93a1947">slave6_err_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00195">195</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="ac04a2a8661ac9a125ab09be2d867674f"></a><!-- doxytag: member="bus_syscon::slave6_dat_o" ref="ac04a2a8661ac9a125ab09be2d867674f" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ac04a2a8661ac9a125ab09be2d867674f">slave6_dat_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00196">196</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a000e51afce7bab2241b4ea4712d3a999"></a><!-- doxytag: member="bus_syscon::slave7_selected" ref="a000e51afce7bab2241b4ea4712d3a999" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a000e51afce7bab2241b4ea4712d3a999">slave7_selected</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00198">198</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="ab3e43099b79ff5eae40e3bf97eb0b1fb"></a><!-- doxytag: member="bus_syscon::slave7_cyc_i" ref="ab3e43099b79ff5eae40e3bf97eb0b1fb" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ab3e43099b79ff5eae40e3bf97eb0b1fb">slave7_cyc_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00199">199</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="ab26afd06e692c9e6fb856700009b152f"></a><!-- doxytag: member="bus_syscon::slave7_stb_i" ref="ab26afd06e692c9e6fb856700009b152f" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ab26afd06e692c9e6fb856700009b152f">slave7_stb_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00200">200</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="ae118b94695ed6a22c4e0d0500dedad7f"></a><!-- doxytag: member="bus_syscon::slave7_ack_o" ref="ae118b94695ed6a22c4e0d0500dedad7f" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ae118b94695ed6a22c4e0d0500dedad7f">slave7_ack_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00201">201</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a32aa24289b7c44cb88038ba3d93b5abb"></a><!-- doxytag: member="bus_syscon::slave7_rty_o" ref="a32aa24289b7c44cb88038ba3d93b5abb" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a32aa24289b7c44cb88038ba3d93b5abb">slave7_rty_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00202">202</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a4a801eeff1c6f96035a872fc8efdfcdf"></a><!-- doxytag: member="bus_syscon::slave7_err_o" ref="a4a801eeff1c6f96035a872fc8efdfcdf" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a4a801eeff1c6f96035a872fc8efdfcdf">slave7_err_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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</table>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00203">203</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="acbfe5025a0ddf90d7ca9714f84927cb7"></a><!-- doxytag: member="bus_syscon::slave7_dat_o" ref="acbfe5025a0ddf90d7ca9714f84927cb7" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#acbfe5025a0ddf90d7ca9714f84927cb7">slave7_dat_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00204">204</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a0f020b9776ff51e66cf86b963fc415f7"></a><!-- doxytag: member="bus_syscon::slave8_selected" ref="a0f020b9776ff51e66cf86b963fc415f7" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a0f020b9776ff51e66cf86b963fc415f7">slave8_selected</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00206">206</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="ae9f79d9b0316cccc84831e4d2fa14b9e"></a><!-- doxytag: member="bus_syscon::slave8_cyc_i" ref="ae9f79d9b0316cccc84831e4d2fa14b9e" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ae9f79d9b0316cccc84831e4d2fa14b9e">slave8_cyc_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00207">207</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="afe4830f4ed051c82a3b156f764124c04"></a><!-- doxytag: member="bus_syscon::slave8_stb_i" ref="afe4830f4ed051c82a3b156f764124c04" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#afe4830f4ed051c82a3b156f764124c04">slave8_stb_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00208">208</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="aed1046a40945768c8d45f62a24c9ed47"></a><!-- doxytag: member="bus_syscon::slave8_ack_o" ref="aed1046a40945768c8d45f62a24c9ed47" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#aed1046a40945768c8d45f62a24c9ed47">slave8_ack_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00209">209</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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</div>
<a class="anchor" id="a27d00f22badadd34aceb9622164e4781"></a><!-- doxytag: member="bus_syscon::slave8_rty_o" ref="a27d00f22badadd34aceb9622164e4781" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a27d00f22badadd34aceb9622164e4781">slave8_rty_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00210">210</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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</div>
<a class="anchor" id="a084aec23fc84531dec6d51ef859477e2"></a><!-- doxytag: member="bus_syscon::slave8_err_o" ref="a084aec23fc84531dec6d51ef859477e2" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a084aec23fc84531dec6d51ef859477e2">slave8_err_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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</table>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00211">211</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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</div>
<a class="anchor" id="a84e433f8ac0985e36b9c3606e13ea64b"></a><!-- doxytag: member="bus_syscon::slave8_dat_o" ref="a84e433f8ac0985e36b9c3606e13ea64b" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a84e433f8ac0985e36b9c3606e13ea64b">slave8_dat_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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</table>
</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00212">212</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a6ceb4d4f0c587250d01040cdd1254681"></a><!-- doxytag: member="bus_syscon::slave9_selected" ref="a6ceb4d4f0c587250d01040cdd1254681" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a6ceb4d4f0c587250d01040cdd1254681">slave9_selected</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00214">214</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a9fc98d5a8298bcfae3cfaecc60de37c7"></a><!-- doxytag: member="bus_syscon::slave9_cyc_i" ref="a9fc98d5a8298bcfae3cfaecc60de37c7" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a9fc98d5a8298bcfae3cfaecc60de37c7">slave9_cyc_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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</table>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00215">215</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="ad8795de1edce0f6eebd93d88d3a92e00"></a><!-- doxytag: member="bus_syscon::slave9_stb_i" ref="ad8795de1edce0f6eebd93d88d3a92e00" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ad8795de1edce0f6eebd93d88d3a92e00">slave9_stb_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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</table>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00216">216</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a2f1ef8dcf5a71370b6cfbf95270512f8"></a><!-- doxytag: member="bus_syscon::slave9_ack_o" ref="a2f1ef8dcf5a71370b6cfbf95270512f8" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a2f1ef8dcf5a71370b6cfbf95270512f8">slave9_ack_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00217">217</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a6eb5262fb37832e37e72a8b1970ffe10"></a><!-- doxytag: member="bus_syscon::slave9_rty_o" ref="a6eb5262fb37832e37e72a8b1970ffe10" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a6eb5262fb37832e37e72a8b1970ffe10">slave9_rty_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00218">218</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="afbb7633bbbeba1f82d8fd30e18ff2524"></a><!-- doxytag: member="bus_syscon::slave9_err_o" ref="afbb7633bbbeba1f82d8fd30e18ff2524" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#afbb7633bbbeba1f82d8fd30e18ff2524">slave9_err_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00219">219</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a5d202044df5f476d04ad99183d215425"></a><!-- doxytag: member="bus_syscon::slave9_dat_o" ref="a5d202044df5f476d04ad99183d215425" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a5d202044df5f476d04ad99183d215425">slave9_dat_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00220">220</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a287d01a9efb78fe9c46648d7255bc1ca"></a><!-- doxytag: member="bus_syscon::slave10_selected" ref="a287d01a9efb78fe9c46648d7255bc1ca" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a287d01a9efb78fe9c46648d7255bc1ca">slave10_selected</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00222">222</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="aa89dca9a069546ad0ee6591c21d91939"></a><!-- doxytag: member="bus_syscon::slave10_cyc_i" ref="aa89dca9a069546ad0ee6591c21d91939" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#aa89dca9a069546ad0ee6591c21d91939">slave10_cyc_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00223">223</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a992d5ff90f3c150f222b715074029145"></a><!-- doxytag: member="bus_syscon::slave10_stb_i" ref="a992d5ff90f3c150f222b715074029145" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a992d5ff90f3c150f222b715074029145">slave10_stb_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00224">224</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="affa0290ff18f1d2161877b94f1acbc82"></a><!-- doxytag: member="bus_syscon::slave10_ack_o" ref="affa0290ff18f1d2161877b94f1acbc82" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#affa0290ff18f1d2161877b94f1acbc82">slave10_ack_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00225">225</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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</div>
<a class="anchor" id="aa2397c1d5ed0b9a1c60683130ebe2cef"></a><!-- doxytag: member="bus_syscon::slave10_rty_o" ref="aa2397c1d5ed0b9a1c60683130ebe2cef" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#aa2397c1d5ed0b9a1c60683130ebe2cef">slave10_rty_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00226">226</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="afb60f7ea4eb65743a5f827edcf834ce0"></a><!-- doxytag: member="bus_syscon::slave10_err_o" ref="afb60f7ea4eb65743a5f827edcf834ce0" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#afb60f7ea4eb65743a5f827edcf834ce0">slave10_err_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00227">227</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a99c3a66fe7640488da6db98c3e45b0cc"></a><!-- doxytag: member="bus_syscon::slave10_dat_o" ref="a99c3a66fe7640488da6db98c3e45b0cc" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a99c3a66fe7640488da6db98c3e45b0cc">slave10_dat_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00228">228</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a78d14b60b06e00903a792ad1d77ff497"></a><!-- doxytag: member="bus_syscon::slave11_selected" ref="a78d14b60b06e00903a792ad1d77ff497" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a78d14b60b06e00903a792ad1d77ff497">slave11_selected</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00230">230</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a0a29a1147b1d162fe08e1497bade580b"></a><!-- doxytag: member="bus_syscon::slave11_cyc_i" ref="a0a29a1147b1d162fe08e1497bade580b" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a0a29a1147b1d162fe08e1497bade580b">slave11_cyc_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00231">231</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="aaada4f622c3960ea0f0093ce8d848d78"></a><!-- doxytag: member="bus_syscon::slave11_stb_i" ref="aaada4f622c3960ea0f0093ce8d848d78" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#aaada4f622c3960ea0f0093ce8d848d78">slave11_stb_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00232">232</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="abb7bd3ab0c61b072f8e9ffd134ffe8d2"></a><!-- doxytag: member="bus_syscon::slave11_ack_o" ref="abb7bd3ab0c61b072f8e9ffd134ffe8d2" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#abb7bd3ab0c61b072f8e9ffd134ffe8d2">slave11_ack_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00233">233</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a9cf033bee86affc16fb9e2b610795c65"></a><!-- doxytag: member="bus_syscon::slave11_rty_o" ref="a9cf033bee86affc16fb9e2b610795c65" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a9cf033bee86affc16fb9e2b610795c65">slave11_rty_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00234">234</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="ac9354d61c84294997c4594b5111600b0"></a><!-- doxytag: member="bus_syscon::slave11_err_o" ref="ac9354d61c84294997c4594b5111600b0" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ac9354d61c84294997c4594b5111600b0">slave11_err_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00235">235</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="ab894d866c396d562c9b78ffac9eef3f9"></a><!-- doxytag: member="bus_syscon::slave11_dat_o" ref="ab894d866c396d562c9b78ffac9eef3f9" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ab894d866c396d562c9b78ffac9eef3f9">slave11_dat_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00236">236</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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</div>
<a class="anchor" id="a3e1451a0c82e45ca9fc968ee359f5d1e"></a><!-- doxytag: member="bus_syscon::slave12_selected" ref="a3e1451a0c82e45ca9fc968ee359f5d1e" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a3e1451a0c82e45ca9fc968ee359f5d1e">slave12_selected</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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</table>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00238">238</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="afe8f4ceaf9e05ef16d37d4f826e0cdab"></a><!-- doxytag: member="bus_syscon::slave12_cyc_i" ref="afe8f4ceaf9e05ef16d37d4f826e0cdab" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#afe8f4ceaf9e05ef16d37d4f826e0cdab">slave12_cyc_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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</table>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00239">239</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="ac9024a113ab36feed7db0780db30bea0"></a><!-- doxytag: member="bus_syscon::slave12_stb_i" ref="ac9024a113ab36feed7db0780db30bea0" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ac9024a113ab36feed7db0780db30bea0">slave12_stb_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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</table>
</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00240">240</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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</div>
<a class="anchor" id="a15fa0aefc995ccf2c646718165ac3dfe"></a><!-- doxytag: member="bus_syscon::slave12_ack_o" ref="a15fa0aefc995ccf2c646718165ac3dfe" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a15fa0aefc995ccf2c646718165ac3dfe">slave12_ack_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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</table>
</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00241">241</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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</div>
<a class="anchor" id="adfc3860ba44fedb9d3090930782dc369"></a><!-- doxytag: member="bus_syscon::slave12_rty_o" ref="adfc3860ba44fedb9d3090930782dc369" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#adfc3860ba44fedb9d3090930782dc369">slave12_rty_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00242">242</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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</div>
<a class="anchor" id="ab79f0b97989c262b0a8611d8dd8c56b1"></a><!-- doxytag: member="bus_syscon::slave12_err_o" ref="ab79f0b97989c262b0a8611d8dd8c56b1" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ab79f0b97989c262b0a8611d8dd8c56b1">slave12_err_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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</table>
</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00243">243</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a37ae46fb6b63a067254daf3ee3c30e6c"></a><!-- doxytag: member="bus_syscon::slave12_dat_o" ref="a37ae46fb6b63a067254daf3ee3c30e6c" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a37ae46fb6b63a067254daf3ee3c30e6c">slave12_dat_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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</table>
</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00244">244</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a9ede6b88ecf28671c42d2cac19a615ce"></a><!-- doxytag: member="bus_syscon::slave13_selected" ref="a9ede6b88ecf28671c42d2cac19a615ce" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a9ede6b88ecf28671c42d2cac19a615ce">slave13_selected</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00246">246</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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</div>
<a class="anchor" id="a1d30c53ac1492a399d5bdcea1f4f9e97"></a><!-- doxytag: member="bus_syscon::slave13_cyc_i" ref="a1d30c53ac1492a399d5bdcea1f4f9e97" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a1d30c53ac1492a399d5bdcea1f4f9e97">slave13_cyc_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00247">247</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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</div>
<a class="anchor" id="a4119edd92ed4bb1094978d07211d8a7e"></a><!-- doxytag: member="bus_syscon::slave13_stb_i" ref="a4119edd92ed4bb1094978d07211d8a7e" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a4119edd92ed4bb1094978d07211d8a7e">slave13_stb_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00248">248</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a4d9a4b357e514701727790e2a2852a13"></a><!-- doxytag: member="bus_syscon::slave13_ack_o" ref="a4d9a4b357e514701727790e2a2852a13" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a4d9a4b357e514701727790e2a2852a13">slave13_ack_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00249">249</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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</div>
<a class="anchor" id="a74dfbb0e1221aaddb9886cda027594b2"></a><!-- doxytag: member="bus_syscon::slave13_rty_o" ref="a74dfbb0e1221aaddb9886cda027594b2" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a74dfbb0e1221aaddb9886cda027594b2">slave13_rty_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00250">250</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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</div>
<a class="anchor" id="a0a1324bfbda7bfcdc87e5fb1ffacf852"></a><!-- doxytag: member="bus_syscon::slave13_err_o" ref="a0a1324bfbda7bfcdc87e5fb1ffacf852" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a0a1324bfbda7bfcdc87e5fb1ffacf852">slave13_err_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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</table>
</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00251">251</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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</div>
<a class="anchor" id="adda20e6b873bffb6ad907fbae1c82861"></a><!-- doxytag: member="bus_syscon::slave13_dat_o" ref="adda20e6b873bffb6ad907fbae1c82861" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#adda20e6b873bffb6ad907fbae1c82861">slave13_dat_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00252">252</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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</div>
<a class="anchor" id="ac7d6549b17e6b3fd88f5d30d1829788b"></a><!-- doxytag: member="bus_syscon::slave14_selected" ref="ac7d6549b17e6b3fd88f5d30d1829788b" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ac7d6549b17e6b3fd88f5d30d1829788b">slave14_selected</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00254">254</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a31f39d555a7cfb0b361993ec13c3fd44"></a><!-- doxytag: member="bus_syscon::slave14_cyc_i" ref="a31f39d555a7cfb0b361993ec13c3fd44" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a31f39d555a7cfb0b361993ec13c3fd44">slave14_cyc_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00255">255</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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</div>
<a class="anchor" id="aa4c036879984d2fc8d7b0dbe4c9342e9"></a><!-- doxytag: member="bus_syscon::slave14_stb_i" ref="aa4c036879984d2fc8d7b0dbe4c9342e9" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#aa4c036879984d2fc8d7b0dbe4c9342e9">slave14_stb_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00256">256</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="ae385e3020186e2bba2b623499dfeee74"></a><!-- doxytag: member="bus_syscon::slave14_ack_o" ref="ae385e3020186e2bba2b623499dfeee74" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ae385e3020186e2bba2b623499dfeee74">slave14_ack_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00257">257</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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</div>
<a class="anchor" id="aa056b5891459a5833a300006fe28635b"></a><!-- doxytag: member="bus_syscon::slave14_rty_o" ref="aa056b5891459a5833a300006fe28635b" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#aa056b5891459a5833a300006fe28635b">slave14_rty_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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</table>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00258">258</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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</div>
<a class="anchor" id="ae7a6494382912bda957d8c6aee681ccb"></a><!-- doxytag: member="bus_syscon::slave14_err_o" ref="ae7a6494382912bda957d8c6aee681ccb" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ae7a6494382912bda957d8c6aee681ccb">slave14_err_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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</table>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00259">259</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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</div>
<a class="anchor" id="a41cfcc25a59e3f3190cf2edb9444ee48"></a><!-- doxytag: member="bus_syscon::slave14_dat_o" ref="a41cfcc25a59e3f3190cf2edb9444ee48" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a41cfcc25a59e3f3190cf2edb9444ee48">slave14_dat_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00260">260</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a1e490ab87c8a474cf171828de8d104e2"></a><!-- doxytag: member="bus_syscon::slave15_selected" ref="a1e490ab87c8a474cf171828de8d104e2" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a1e490ab87c8a474cf171828de8d104e2">slave15_selected</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00262">262</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a53dc2da305fb7ab39b9818828071aea0"></a><!-- doxytag: member="bus_syscon::slave15_cyc_i" ref="a53dc2da305fb7ab39b9818828071aea0" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a53dc2da305fb7ab39b9818828071aea0">slave15_cyc_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00263">263</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="ad30a385cac2f1d80e01a121cb44f21a8"></a><!-- doxytag: member="bus_syscon::slave15_stb_i" ref="ad30a385cac2f1d80e01a121cb44f21a8" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ad30a385cac2f1d80e01a121cb44f21a8">slave15_stb_i</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00264">264</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a2d91fbf38458701a03ccc89ec6aaf9e7"></a><!-- doxytag: member="bus_syscon::slave15_ack_o" ref="a2d91fbf38458701a03ccc89ec6aaf9e7" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a2d91fbf38458701a03ccc89ec6aaf9e7">slave15_ack_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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</table>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00265">265</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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</div>
<a class="anchor" id="a7a482ec8b3e015ef00659e3557bf19df"></a><!-- doxytag: member="bus_syscon::slave15_rty_o" ref="a7a482ec8b3e015ef00659e3557bf19df" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a7a482ec8b3e015ef00659e3557bf19df">slave15_rty_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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</table>
</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00266">266</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a284bad867d4e58188b2aa72441bd9334"></a><!-- doxytag: member="bus_syscon::slave15_err_o" ref="a284bad867d4e58188b2aa72441bd9334" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a284bad867d4e58188b2aa72441bd9334">slave15_err_o</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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</table>
</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00267">267</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="ad02d85c84ccfddd7e7488e8a0b009388"></a><!-- doxytag: member="bus_syscon::slave15_dat_o" ref="ad02d85c84ccfddd7e7488e8a0b009388" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#ad02d85c84ccfddd7e7488e8a0b009388">slave15_dat_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00268">268</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="aff069d1a7ae0371a0399bddf16d12abe"></a><!-- doxytag: member="bus_syscon::debug_syscon" ref="aff069d1a7ae0371a0399bddf16d12abe" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#aff069d1a7ae0371a0399bddf16d12abe">debug_syscon</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">7</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00272">272</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a9eb95d18c5053aab98fa0660e06d80cc"></a><!-- doxytag: member="bus_syscon::master_cyc_stb_o" ref="a9eb95d18c5053aab98fa0660e06d80cc" args="wire" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a9eb95d18c5053aab98fa0660e06d80cc">master_cyc_stb_o</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00316">316</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a637fb5d32d290c5e04b4b6c1144caaa8"></a><!-- doxytag: member="bus_syscon::slave0_selected" ref="a637fb5d32d290c5e04b4b6c1144caaa8" args="wire" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a637fb5d32d290c5e04b4b6c1144caaa8">slave0_selected</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00358">358</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a14f9b22c806a4c54dff9a30bec68388b"></a><!-- doxytag: member="bus_syscon::master_ack_i" ref="a14f9b22c806a4c54dff9a30bec68388b" args="wire" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a14f9b22c806a4c54dff9a30bec68388b">master_ack_i</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00411">411</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a5b8736c002bf69e8ddd80782643b650e"></a><!-- doxytag: member="bus_syscon::master_rty_i" ref="a5b8736c002bf69e8ddd80782643b650e" args="wire" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a5b8736c002bf69e8ddd80782643b650e">master_rty_i</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire]</code></td>
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<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00428">428</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="abdcb59d4119f1071d644221a16e0db35"></a><!-- doxytag: member="bus_syscon::master_err_i" ref="abdcb59d4119f1071d644221a16e0db35" args="wire" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#abdcb59d4119f1071d644221a16e0db35">master_err_i</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire]</code></td>
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<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00445">445</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a32e1a6ae3e2bf599f8a83c1241422eb3"></a><!-- doxytag: member="bus_syscon::last_master" ref="a32e1a6ae3e2bf599f8a83c1241422eb3" args="wire[4:0]" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a32e1a6ae3e2bf599f8a83c1241422eb3">last_master</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[4:0]]</code></td>
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<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00463">463</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<a class="anchor" id="a1b655884a9784b2977272cc44dc8da80"></a><!-- doxytag: member="bus_syscon::last_master_reg" ref="a1b655884a9784b2977272cc44dc8da80" args="reg[4:0]" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__syscon.html#a1b655884a9784b2977272cc44dc8da80">last_master_reg</a></span> <b><span class="vhdlchar"> </span></b> <code> [reg[4:0]]</code></td>
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<p>Definition at line <a class="el" href="bus__syscon_8v_source.html#l00600">600</a> of file <a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a>.</p>
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<hr/>The documentation for this class was generated from the following file:<ul>
<li><a class="el" href="bus__syscon_8v_source.html">bus_syscon.v</a></li>
</ul>
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<hr class="footer"/><address class="footer"><small>Generated on Mon Dec 20 2010 21:20:20 for aoOCS by 
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<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.2 </small></address>
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