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<h1>bus_terminator Module Reference</h1> </div>
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<!-- doxytag: class="bus_terminator" -->
<p><p>Terminator for not handled WISHBONE bus cycles. </p>
<a href="#_details">More...</a></p>
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Inheritance diagram for bus_terminator:<!-- endSectionHeader --></div>
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<p><a href="classbus__terminator-members.html">List of all members.</a></p>
<table class="memberdecls">
<tr><td colspan="2"><h2><a name="Always Constructs"></a>
Always Constructs</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__terminator.html#a0c661acb3f7be5a11a46134c7fb9d7b2">ALWAYS_34</a> </td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classbus__terminator.html#a504389b095a9baf2f88945340e64c4ab">CLK_I</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classbus__terminator.html#a0e510f9c4f5e9af32ea1636b00cfb952">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
<tr><td colspan="2"><h2><a name="Inputs"></a>
Inputs</h2></td></tr>
<tr><td colspan="2"><div class="groupHeader">Clock and reset</div></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__terminator.html#a504389b095a9baf2f88945340e64c4ab">CLK_I</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__terminator.html#a0e510f9c4f5e9af32ea1636b00cfb952">reset_n</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td colspan="2"><div class="groupHeader">WISHBONE slave</div></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__terminator.html#ae78ac8eb886aa627384f63905a5e29e5">ADR_I</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">2</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__terminator.html#a596ac126fa1168b2d59936d3c9778deb">CYC_I</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__terminator.html#a31e187f84a3ea1a4e4cd377141a3f19e">WE_I</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__terminator.html#ae3ce51f791c566e098e7d558290e7366">STB_I</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__terminator.html#a994f936ec3b678f3e4bff3cfa2256390">SEL_I</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__terminator.html#a00620d44f29f18431e1b9e2a889f72a9">slave_DAT_I</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td colspan="2"><div class="groupHeader">ao68000 interrupt cycle indicator</div></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__terminator.html#ab33b4e390a6cca8ffc2af080d219b48a">cpu_space_cycle</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td colspan="2"><h2><a name="Outputs"></a>
Outputs</h2></td></tr>
<tr><td colspan="2"><div class="groupHeader">WISHBONE slave</div></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__terminator.html#a398652206e0fb61250ca64834cc4c825">slave_DAT_O</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__terminator.html#aa6bce0ee76b21cf32566499eb19c2861">ACK_O</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__terminator.html#af69c7a0cbf74d76a0736a758ee74c7f1">RTY_O</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__terminator.html#a9b755e92f028d4f9a9534124fbc73913">ERR_O</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td colspan="2"><h2><a name="Signals"></a>
Signals</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classbus__terminator.html#aefdadc25d9b399769ec9b68788ce1aab">accepted_addresses</a> </td></tr>
</table>
<hr/><a name="_details"></a><h2>Detailed Description</h2>
<p>Terminator for not handled WISHBONE bus cycles. </p>
<p>Definition at line <a class="el" href="bus__terminator_8v_source.html#l00031">31</a> of file <a class="el" href="bus__terminator_8v_source.html">bus_terminator.v</a>.</p>
<hr/><h2>Member Function Documentation</h2>
<a class="anchor" id="a0c661acb3f7be5a11a46134c7fb9d7b2"></a><!-- doxytag: member="bus_terminator::ALWAYS_34" ref="a0c661acb3f7be5a11a46134c7fb9d7b2" args="CLK_I, reset_n" -->
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<td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_34 <td></td>
<td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classbus__terminator.html#a504389b095a9baf2f88945340e64c4ab">CLK_I</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> , </td>
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<td class="paramkey"></td>
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<td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classbus__terminator.html#a0e510f9c4f5e9af32ea1636b00cfb952">reset_n</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> ) </td>
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<code> [Always Construct]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__terminator_8v_source.html#l00075">75</a> of file <a class="el" href="bus__terminator_8v_source.html">bus_terminator.v</a>.</p>
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<hr/><h2>Member Data Documentation</h2>
<a class="anchor" id="a504389b095a9baf2f88945340e64c4ab"></a><!-- doxytag: member="bus_terminator::CLK_I" ref="a504389b095a9baf2f88945340e64c4ab" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__terminator.html#a504389b095a9baf2f88945340e64c4ab">CLK_I</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__terminator_8v_source.html#l00034">34</a> of file <a class="el" href="bus__terminator_8v_source.html">bus_terminator.v</a>.</p>
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<a class="anchor" id="a0e510f9c4f5e9af32ea1636b00cfb952"></a><!-- doxytag: member="bus_terminator::reset_n" ref="a0e510f9c4f5e9af32ea1636b00cfb952" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__terminator.html#a0e510f9c4f5e9af32ea1636b00cfb952">reset_n</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__terminator_8v_source.html#l00035">35</a> of file <a class="el" href="bus__terminator_8v_source.html">bus_terminator.v</a>.</p>
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<a class="anchor" id="ae78ac8eb886aa627384f63905a5e29e5"></a><!-- doxytag: member="bus_terminator::ADR_I" ref="ae78ac8eb886aa627384f63905a5e29e5" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__terminator.html#ae78ac8eb886aa627384f63905a5e29e5">ADR_I</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">2</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__terminator_8v_source.html#l00040">40</a> of file <a class="el" href="bus__terminator_8v_source.html">bus_terminator.v</a>.</p>
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<a class="anchor" id="a596ac126fa1168b2d59936d3c9778deb"></a><!-- doxytag: member="bus_terminator::CYC_I" ref="a596ac126fa1168b2d59936d3c9778deb" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__terminator.html#a596ac126fa1168b2d59936d3c9778deb">CYC_I</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__terminator_8v_source.html#l00041">41</a> of file <a class="el" href="bus__terminator_8v_source.html">bus_terminator.v</a>.</p>
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<a class="anchor" id="a31e187f84a3ea1a4e4cd377141a3f19e"></a><!-- doxytag: member="bus_terminator::WE_I" ref="a31e187f84a3ea1a4e4cd377141a3f19e" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__terminator.html#a31e187f84a3ea1a4e4cd377141a3f19e">WE_I</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__terminator_8v_source.html#l00042">42</a> of file <a class="el" href="bus__terminator_8v_source.html">bus_terminator.v</a>.</p>
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<a class="anchor" id="ae3ce51f791c566e098e7d558290e7366"></a><!-- doxytag: member="bus_terminator::STB_I" ref="ae3ce51f791c566e098e7d558290e7366" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__terminator.html#ae3ce51f791c566e098e7d558290e7366">STB_I</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__terminator_8v_source.html#l00043">43</a> of file <a class="el" href="bus__terminator_8v_source.html">bus_terminator.v</a>.</p>
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<a class="anchor" id="a994f936ec3b678f3e4bff3cfa2256390"></a><!-- doxytag: member="bus_terminator::SEL_I" ref="a994f936ec3b678f3e4bff3cfa2256390" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__terminator.html#a994f936ec3b678f3e4bff3cfa2256390">SEL_I</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__terminator_8v_source.html#l00044">44</a> of file <a class="el" href="bus__terminator_8v_source.html">bus_terminator.v</a>.</p>
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<a class="anchor" id="a00620d44f29f18431e1b9e2a889f72a9"></a><!-- doxytag: member="bus_terminator::slave_DAT_I" ref="a00620d44f29f18431e1b9e2a889f72a9" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__terminator.html#a00620d44f29f18431e1b9e2a889f72a9">slave_DAT_I</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__terminator_8v_source.html#l00045">45</a> of file <a class="el" href="bus__terminator_8v_source.html">bus_terminator.v</a>.</p>
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<a class="anchor" id="a398652206e0fb61250ca64834cc4c825"></a><!-- doxytag: member="bus_terminator::slave_DAT_O" ref="a398652206e0fb61250ca64834cc4c825" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__terminator.html#a398652206e0fb61250ca64834cc4c825">slave_DAT_O</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__terminator_8v_source.html#l00046">46</a> of file <a class="el" href="bus__terminator_8v_source.html">bus_terminator.v</a>.</p>
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<a class="anchor" id="aa6bce0ee76b21cf32566499eb19c2861"></a><!-- doxytag: member="bus_terminator::ACK_O" ref="aa6bce0ee76b21cf32566499eb19c2861" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__terminator.html#aa6bce0ee76b21cf32566499eb19c2861">ACK_O</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__terminator_8v_source.html#l00047">47</a> of file <a class="el" href="bus__terminator_8v_source.html">bus_terminator.v</a>.</p>
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<a class="anchor" id="af69c7a0cbf74d76a0736a758ee74c7f1"></a><!-- doxytag: member="bus_terminator::RTY_O" ref="af69c7a0cbf74d76a0736a758ee74c7f1" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__terminator.html#af69c7a0cbf74d76a0736a758ee74c7f1">RTY_O</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__terminator_8v_source.html#l00048">48</a> of file <a class="el" href="bus__terminator_8v_source.html">bus_terminator.v</a>.</p>
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<a class="anchor" id="a9b755e92f028d4f9a9534124fbc73913"></a><!-- doxytag: member="bus_terminator::ERR_O" ref="a9b755e92f028d4f9a9534124fbc73913" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__terminator.html#a9b755e92f028d4f9a9534124fbc73913">ERR_O</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__terminator_8v_source.html#l00049">49</a> of file <a class="el" href="bus__terminator_8v_source.html">bus_terminator.v</a>.</p>
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<a class="anchor" id="ab33b4e390a6cca8ffc2af080d219b48a"></a><!-- doxytag: member="bus_terminator::cpu_space_cycle" ref="ab33b4e390a6cca8ffc2af080d219b48a" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__terminator.html#ab33b4e390a6cca8ffc2af080d219b48a">cpu_space_cycle</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="bus__terminator_8v_source.html#l00054">54</a> of file <a class="el" href="bus__terminator_8v_source.html">bus_terminator.v</a>.</p>
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<a class="anchor" id="aefdadc25d9b399769ec9b68788ce1aab"></a><!-- doxytag: member="bus_terminator::accepted_addresses" ref="aefdadc25d9b399769ec9b68788ce1aab" args="wire" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__terminator.html#aefdadc25d9b399769ec9b68788ce1aab">accepted_addresses</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire]</code></td>
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<p>Definition at line <a class="el" href="bus__terminator_8v_source.html#l00061">61</a> of file <a class="el" href="bus__terminator_8v_source.html">bus_terminator.v</a>.</p>
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<hr/>The documentation for this class was generated from the following file:<ul>
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