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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> <html xmlns="http://www.w3.org/1999/xhtml"> <head> <meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> <title>aoOCS: debug Module Reference</title> <link href="tabs.css" rel="stylesheet" type="text/css"/> <link href="doxygen.css" rel="stylesheet" type="text/css"/> </head> <body> <!-- Generated by Doxygen 1.7.2 --> <div class="navigation" id="top"> <div class="tabs"> <ul class="tablist"> <li><a href="index.html"><span>Main Page</span></a></li> <li><a href="modules.html"><span>Modules</span></a></li> <li class="current"><a href="annotated.html"><span>Design Unit List</span></a></li> <li><a href="files.html"><span>Files</span></a></li> </ul> </div> <div class="tabs2"> <ul class="tablist"> <li><a href="annotated.html"><span>Class List</span></a></li> <li><a href="hierarchy.html"><span>Design Unit Hierarchy</span></a></li> <li><a href="functions.html"><span>Design Unit Members</span></a></li> </ul> </div> </div> <div class="header"> <div class="summary"> <a href="#Inputs">Inputs</a> | <a href="#Outputs">Outputs</a> | <a href="#Signals">Signals</a> | <a href="#Always Constructs">Always Constructs</a> </div> <div class="headertitle"> <h1>debug Module Reference</h1> </div> </div> <div class="contents"> <!-- doxytag: class="debug" --> <p><p>Switches and hex leds driver for debug purposes. </p> <a href="#_details">More...</a></p> <p><a href="classdebug-members.html">List of all members.</a></p> <table class="memberdecls"> <tr><td colspan="2"><h2><a name="Always Constructs"></a> Always Constructs</h2></td></tr> <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classdebug.html#a4d3363cafc055d3a43d966b389c9e1eb">ALWAYS_67</a> </td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classdebug.html#a1a57b205e7466b8d50a32941fba4ab48">CLK_I</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classdebug.html#a978b9adc0d5eac44623b770fd5747abb">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr> <tr><td colspan="2"><h2><a name="Inputs"></a> Inputs</h2></td></tr> <tr><td colspan="2"><div class="groupHeader">Clock and reset</div></td></tr> <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classdebug.html#a1a57b205e7466b8d50a32941fba4ab48">CLK_I</a>  </td><td class="memItemRight" valign="bottom"></td></tr> <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classdebug.html#a978b9adc0d5eac44623b770fd5747abb">reset_n</a>  </td><td class="memItemRight" valign="bottom"></td></tr> <tr><td colspan="2"><div class="groupHeader">Internal debug signals</div></td></tr> <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classdebug.html#a68a193ffd2ee63ac4afd94918d029e3f">master_adr_o</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">2</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr> <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classdebug.html#a39b9c01ea045877762a89b7fc1a2e26b">debug_pc</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr> <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classdebug.html#a8ffb737f12841af377f3aeed58876e73">debug_syscon</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">7</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr> <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classdebug.html#ab518991b1a3be5ae3e9ee52778c64edc">debug_track</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">7</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr> <tr><td colspan="2"><div class="groupHeader">Switches and hex leds hardware interface</div></td></tr> <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classdebug.html#a458c757b688287338fd4f33d350a693b">debug_sw_pc</a>  </td><td class="memItemRight" valign="bottom"></td></tr> <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classdebug.html#a3928f624e2dd722d2a22232c17eccead">debug_sw_adr</a>  </td><td class="memItemRight" valign="bottom"></td></tr> <tr><td colspan="2"><h2><a name="Outputs"></a> Outputs</h2></td></tr> <tr><td colspan="2"><div class="groupHeader">Switches and hex leds hardware interface</div></td></tr> <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classdebug.html#ab60f92c8fe053a023d88b8a16c5d8381">hex0</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">7</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr> <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classdebug.html#a90b2f3a81df208e060f8b1f272cfe316">hex1</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">7</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr> <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classdebug.html#a2882688fc07d211c2faa31f270496d19">hex2</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">7</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr> <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classdebug.html#a47a9670ed950738e8f9092745cc5db29">hex3</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">7</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr> <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classdebug.html#ae7290a5819cd1917a87ede5216ba5319">hex4</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">7</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr> <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classdebug.html#a930292ade8440aa0192221872bd9eb51">hex5</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">7</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr> <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classdebug.html#a5bde1191353631135896e66d2610e500">hex6</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">7</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr> <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classdebug.html#ad42ffb89cd4342a555c855f8ffeeae43">hex7</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">7</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr> <tr><td colspan="2"><h2><a name="Signals"></a> Signals</h2></td></tr> <tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classdebug.html#a74ab966a3276a0d188a148a14dba6670">display</a> </td></tr> </table> <hr/><a name="_details"></a><h2>Detailed Description</h2> <p>Switches and hex leds driver for debug purposes. </p> <p>Definition at line <a class="el" href="drv__debug_8v_source.html#l00031">31</a> of file <a class="el" href="drv__debug_8v_source.html">drv_debug.v</a>.</p> <hr/><h2>Member Function Documentation</h2> <a class="anchor" id="a4d3363cafc055d3a43d966b389c9e1eb"></a><!-- doxytag: member="debug::ALWAYS_67" ref="a4d3363cafc055d3a43d966b389c9e1eb" args="CLK_I, reset_n" --> <div class="memitem"> <div class="memproto"> <table class="memname"> <tr> <td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_67 <td></td> <td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classdebug.html#a1a57b205e7466b8d50a32941fba4ab48">CLK_I</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> , </td> </tr> <tr> <td class="paramkey"></td> <td></td> <td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classdebug.html#a978b9adc0d5eac44623b770fd5747abb">reset_n</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> ) </td> </tr> <code> [Always Construct]</code></td> </tr> </table> </div> <div class="memdoc"> <p>Definition at line <a class="el" href="drv__debug_8v_source.html#l00201">201</a> of file <a class="el" href="drv__debug_8v_source.html">drv_debug.v</a>.</p> </div> </div> <hr/><h2>Member Data Documentation</h2> <a class="anchor" id="a1a57b205e7466b8d50a32941fba4ab48"></a><!-- doxytag: member="debug::CLK_I" ref="a1a57b205e7466b8d50a32941fba4ab48" args="" --> <div class="memitem"> <div class="memproto"> <table class="memname"> <tr> <td class="memname"><span class="stringliteral"><a class="el" href="classdebug.html#a1a57b205e7466b8d50a32941fba4ab48">CLK_I</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td> </tr> </table> </div> <div class="memdoc"> <p>Definition at line <a class="el" href="drv__debug_8v_source.html#l00034">34</a> of file <a class="el" href="drv__debug_8v_source.html">drv_debug.v</a>.</p> </div> </div> <a class="anchor" id="a978b9adc0d5eac44623b770fd5747abb"></a><!-- doxytag: member="debug::reset_n" ref="a978b9adc0d5eac44623b770fd5747abb" args="" --> <div class="memitem"> <div class="memproto"> <table class="memname"> <tr> <td class="memname"><span class="stringliteral"><a class="el" href="classdebug.html#a978b9adc0d5eac44623b770fd5747abb">reset_n</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td> </tr> </table> </div> <div class="memdoc"> <p>Definition at line <a class="el" href="drv__debug_8v_source.html#l00035">35</a> of file <a class="el" href="drv__debug_8v_source.html">drv_debug.v</a>.</p> </div> </div> <a class="anchor" id="a68a193ffd2ee63ac4afd94918d029e3f"></a><!-- doxytag: member="debug::master_adr_o" ref="a68a193ffd2ee63ac4afd94918d029e3f" args="" --> <div class="memitem"> <div class="memproto"> <table class="memname"> <tr> <td class="memname"><span class="stringliteral"><a class="el" href="classdebug.html#a68a193ffd2ee63ac4afd94918d029e3f">master_adr_o</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">2</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td> </tr> </table> </div> <div class="memdoc"> <p>Definition at line <a class="el" href="drv__debug_8v_source.html#l00040">40</a> of file <a class="el" href="drv__debug_8v_source.html">drv_debug.v</a>.</p> </div> </div> <a class="anchor" id="a39b9c01ea045877762a89b7fc1a2e26b"></a><!-- doxytag: member="debug::debug_pc" ref="a39b9c01ea045877762a89b7fc1a2e26b" args="" --> <div class="memitem"> <div class="memproto"> <table class="memname"> <tr> <td class="memname"><span class="stringliteral"><a class="el" href="classdebug.html#a39b9c01ea045877762a89b7fc1a2e26b">debug_pc</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td> </tr> </table> </div> <div class="memdoc"> <p>Definition at line <a class="el" href="drv__debug_8v_source.html#l00041">41</a> of file <a class="el" href="drv__debug_8v_source.html">drv_debug.v</a>.</p> </div> </div> <a class="anchor" id="a8ffb737f12841af377f3aeed58876e73"></a><!-- doxytag: member="debug::debug_syscon" ref="a8ffb737f12841af377f3aeed58876e73" args="" --> <div class="memitem"> <div class="memproto"> <table class="memname"> <tr> <td class="memname"><span class="stringliteral"><a class="el" href="classdebug.html#a8ffb737f12841af377f3aeed58876e73">debug_syscon</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">7</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td> </tr> </table> </div> <div class="memdoc"> <p>Definition at line <a class="el" href="drv__debug_8v_source.html#l00042">42</a> of file <a class="el" href="drv__debug_8v_source.html">drv_debug.v</a>.</p> </div> </div> <a class="anchor" id="ab518991b1a3be5ae3e9ee52778c64edc"></a><!-- doxytag: member="debug::debug_track" ref="ab518991b1a3be5ae3e9ee52778c64edc" args="" --> <div class="memitem"> <div class="memproto"> <table class="memname"> <tr> <td class="memname"><span class="stringliteral"><a class="el" href="classdebug.html#ab518991b1a3be5ae3e9ee52778c64edc">debug_track</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">7</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td> </tr> </table> </div> <div class="memdoc"> <p>Definition at line <a class="el" href="drv__debug_8v_source.html#l00043">43</a> of file <a class="el" href="drv__debug_8v_source.html">drv_debug.v</a>.</p> </div> </div> <a class="anchor" id="ab60f92c8fe053a023d88b8a16c5d8381"></a><!-- doxytag: member="debug::hex0" ref="ab60f92c8fe053a023d88b8a16c5d8381" args="" --> <div class="memitem"> <div class="memproto"> <table class="memname"> <tr> <td class="memname"><span class="stringliteral"><a class="el" href="classdebug.html#ab60f92c8fe053a023d88b8a16c5d8381">hex0</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">7</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td> </tr> </table> </div> <div class="memdoc"> <p>Definition at line <a class="el" href="drv__debug_8v_source.html#l00049">49</a> of file <a class="el" href="drv__debug_8v_source.html">drv_debug.v</a>.</p> </div> </div> <a class="anchor" id="a90b2f3a81df208e060f8b1f272cfe316"></a><!-- doxytag: member="debug::hex1" ref="a90b2f3a81df208e060f8b1f272cfe316" args="" --> <div class="memitem"> <div class="memproto"> <table class="memname"> <tr> <td class="memname"><span class="stringliteral"><a class="el" href="classdebug.html#a90b2f3a81df208e060f8b1f272cfe316">hex1</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">7</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td> </tr> </table> </div> <div class="memdoc"> <p>Definition at line <a class="el" href="drv__debug_8v_source.html#l00050">50</a> of file <a class="el" href="drv__debug_8v_source.html">drv_debug.v</a>.</p> </div> </div> <a class="anchor" id="a2882688fc07d211c2faa31f270496d19"></a><!-- doxytag: member="debug::hex2" ref="a2882688fc07d211c2faa31f270496d19" args="" --> <div class="memitem"> <div class="memproto"> <table class="memname"> <tr> <td class="memname"><span class="stringliteral"><a class="el" href="classdebug.html#a2882688fc07d211c2faa31f270496d19">hex2</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">7</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td> </tr> </table> </div> <div class="memdoc"> <p>Definition at line <a class="el" href="drv__debug_8v_source.html#l00051">51</a> of file <a class="el" href="drv__debug_8v_source.html">drv_debug.v</a>.</p> </div> </div> <a class="anchor" id="a47a9670ed950738e8f9092745cc5db29"></a><!-- doxytag: member="debug::hex3" ref="a47a9670ed950738e8f9092745cc5db29" args="" --> <div class="memitem"> <div class="memproto"> <table class="memname"> <tr> <td class="memname"><span class="stringliteral"><a class="el" href="classdebug.html#a47a9670ed950738e8f9092745cc5db29">hex3</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">7</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td> </tr> </table> </div> <div class="memdoc"> <p>Definition at line <a class="el" href="drv__debug_8v_source.html#l00052">52</a> of file <a class="el" href="drv__debug_8v_source.html">drv_debug.v</a>.</p> </div> </div> <a class="anchor" id="ae7290a5819cd1917a87ede5216ba5319"></a><!-- doxytag: member="debug::hex4" ref="ae7290a5819cd1917a87ede5216ba5319" args="" --> <div class="memitem"> <div class="memproto"> <table class="memname"> <tr> <td class="memname"><span class="stringliteral"><a class="el" href="classdebug.html#ae7290a5819cd1917a87ede5216ba5319">hex4</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">7</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td> </tr> </table> </div> <div class="memdoc"> <p>Definition at line <a class="el" href="drv__debug_8v_source.html#l00053">53</a> of file <a class="el" href="drv__debug_8v_source.html">drv_debug.v</a>.</p> </div> </div> <a class="anchor" id="a930292ade8440aa0192221872bd9eb51"></a><!-- doxytag: member="debug::hex5" ref="a930292ade8440aa0192221872bd9eb51" args="" --> <div class="memitem"> <div class="memproto"> <table class="memname"> <tr> <td class="memname"><span class="stringliteral"><a class="el" href="classdebug.html#a930292ade8440aa0192221872bd9eb51">hex5</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">7</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td> </tr> </table> </div> <div class="memdoc"> <p>Definition at line <a class="el" href="drv__debug_8v_source.html#l00054">54</a> of file <a class="el" href="drv__debug_8v_source.html">drv_debug.v</a>.</p> </div> </div> <a class="anchor" id="a5bde1191353631135896e66d2610e500"></a><!-- doxytag: member="debug::hex6" ref="a5bde1191353631135896e66d2610e500" args="" --> <div class="memitem"> <div class="memproto"> <table class="memname"> <tr> <td class="memname"><span class="stringliteral"><a class="el" href="classdebug.html#a5bde1191353631135896e66d2610e500">hex6</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">7</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td> </tr> </table> </div> <div class="memdoc"> <p>Definition at line <a class="el" href="drv__debug_8v_source.html#l00055">55</a> of file <a class="el" href="drv__debug_8v_source.html">drv_debug.v</a>.</p> </div> </div> <a class="anchor" id="ad42ffb89cd4342a555c855f8ffeeae43"></a><!-- doxytag: member="debug::hex7" ref="ad42ffb89cd4342a555c855f8ffeeae43" args="" --> <div class="memitem"> <div class="memproto"> <table class="memname"> <tr> <td class="memname"><span class="stringliteral"><a class="el" href="classdebug.html#ad42ffb89cd4342a555c855f8ffeeae43">hex7</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">7</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td> </tr> </table> </div> <div class="memdoc"> <p>Definition at line <a class="el" href="drv__debug_8v_source.html#l00056">56</a> of file <a class="el" href="drv__debug_8v_source.html">drv_debug.v</a>.</p> </div> </div> <a class="anchor" id="a458c757b688287338fd4f33d350a693b"></a><!-- doxytag: member="debug::debug_sw_pc" ref="a458c757b688287338fd4f33d350a693b" args="" --> <div class="memitem"> <div class="memproto"> <table class="memname"> <tr> <td class="memname"><span class="stringliteral"><a class="el" href="classdebug.html#a458c757b688287338fd4f33d350a693b">debug_sw_pc</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td> </tr> </table> </div> <div class="memdoc"> <p>Definition at line <a class="el" href="drv__debug_8v_source.html#l00058">58</a> of file <a class="el" href="drv__debug_8v_source.html">drv_debug.v</a>.</p> </div> </div> <a class="anchor" id="a3928f624e2dd722d2a22232c17eccead"></a><!-- doxytag: member="debug::debug_sw_adr" ref="a3928f624e2dd722d2a22232c17eccead" args="" --> <div class="memitem"> <div class="memproto"> <table class="memname"> <tr> <td class="memname"><span class="stringliteral"><a class="el" href="classdebug.html#a3928f624e2dd722d2a22232c17eccead">debug_sw_adr</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td> </tr> </table> </div> <div class="memdoc"> <p>Definition at line <a class="el" href="drv__debug_8v_source.html#l00059">59</a> of file <a class="el" href="drv__debug_8v_source.html">drv_debug.v</a>.</p> </div> </div> <a class="anchor" id="a74ab966a3276a0d188a148a14dba6670"></a><!-- doxytag: member="debug::display" ref="a74ab966a3276a0d188a148a14dba6670" args="reg[31:0]" --> <div class="memitem"> <div class="memproto"> <table class="memname"> <tr> <td class="memname"><span class="stringliteral"><a class="el" href="classdebug.html#a74ab966a3276a0d188a148a14dba6670">display</a></span> <b><span class="vhdlchar"> </span></b> <code> [reg[31:0]]</code></td> </tr> </table> </div> <div class="memdoc"> <p>Definition at line <a class="el" href="drv__debug_8v_source.html#l00199">199</a> of file <a class="el" href="drv__debug_8v_source.html">drv_debug.v</a>.</p> </div> </div> <hr/>The documentation for this class was generated from the following file:<ul> <li><a class="el" href="drv__debug_8v_source.html">drv_debug.v</a></li> </ul> </div> <hr class="footer"/><address class="footer"><small>Generated on Sun Dec 19 2010 11:29:45 for aoOCS by  <a href="http://www.doxygen.org/index.html"> <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.2 </small></address> </body> </html>