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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> <html xmlns="http://www.w3.org/1999/xhtml"> <head> <meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> <title>aoOCS: memory_registers Module Reference</title> <link href="tabs.css" rel="stylesheet" type="text/css"/> <link href="doxygen.css" rel="stylesheet" type="text/css"/> </head> <body> <!-- Generated by Doxygen 1.7.2 --> <div class="navigation" id="top"> <div class="tabs"> <ul class="tablist"> <li><a href="index.html"><span>Main Page</span></a></li> <li class="current"><a href="annotated.html"><span>Design Unit List</span></a></li> <li><a href="files.html"><span>Files</span></a></li> </ul> </div> <div class="tabs2"> <ul class="tablist"> <li><a href="annotated.html"><span>Class List</span></a></li> <li><a href="hierarchy.html"><span>Design Unit Hierarchy</span></a></li> <li><a href="functions.html"><span>Design Unit Members</span></a></li> </ul> </div> </div> <div class="header"> <div class="summary"> <a href="#Inputs">Inputs</a> | <a href="#Outputs">Outputs</a> | <a href="#Signals">Signals</a> | <a href="#Module Instances">Module Instances</a> | <a href="#Always Constructs">Always Constructs</a> </div> <div class="headertitle"> <h1>memory_registers Module Reference</h1> </div> </div> <div class="contents"> <!-- doxytag: class="memory_registers" --> <p>Contains the microcode ROM and D0-D7, A0-A7 registers. <a href="#_details">More...</a></p> <!-- startSectionHeader --><div class="dynheader"> Inheritance diagram for memory_registers:<!-- endSectionHeader --></div> <!-- startSectionSummary --><!-- endSectionSummary --><!-- startSectionContent --><div class="dyncontent"> <div class="center"> <img src="classmemory__registers.png" usemap="#memory_registers_map" alt=""/> <map id="memory_registers_map" name="memory_registers_map"> <area href="classao68000.html" alt="ao68000" shape="rect" coords="0,56,112,80"/> <area href="classaoOCS.html" alt="aoOCS" shape="rect" coords="0,112,112,136"/> </map> </div><!-- endSectionContent --></div> <p><a href="classmemory__registers-members.html">List of all members.</a></p> <table class="memberdecls"> <tr><td colspan="2"><h2><a name="Always Constructs"></a> Always Constructs</h2></td></tr> <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a09281e3224878c570c81844785844fe0">ALWAYS_29</a> </td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classmemory__registers.html#a30d6f9a116a35132d3ae1ac844480c7f">clock</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classmemory__registers.html#a0070367d69af978092b5cd0b60dec77b">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr> <tr><td colspan="2"><h2><a name="Inputs"></a> Inputs</h2></td></tr> <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a30d6f9a116a35132d3ae1ac844480c7f">clock</a>  </td><td class="memItemRight" valign="bottom"></td></tr> <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a0070367d69af978092b5cd0b60dec77b">reset_n</a>  </td><td class="memItemRight" valign="bottom"></td></tr> <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#af3fdc1a826e2d4992fc50550160eed52">An_address</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr> <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a05d2b0cd0706cfcb62674e59ed049b22">An_input</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr> <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#abfa12b67b2dfb6da21584304919f0a15">An_write_enable</a>  </td><td class="memItemRight" valign="bottom"></td></tr> <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a55db549a365e2da7b32c589888f22c1f">Dn_address</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr> <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a70e26deed20065da35879d3ce4a7f06e">Dn_input</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr> <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a515d2e4fc82f04802e46d5eae5d0f0f5">Dn_write_enable</a>  </td><td class="memItemRight" valign="bottom"></td></tr> <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a7e475d550020f2ef86841dd171ddf94e">Dn_size</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">1</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr> <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a242c22630fbc44df8a129350db77b3d0">micro_pc</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">8</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr> <tr><td colspan="2"><h2><a name="Outputs"></a> Outputs</h2></td></tr> <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#afe969a18dcdd487deeedc9f9146ef8c9">An_output</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr> <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a3380b9a07ee51a05b97308d5a7257972">usp</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr> <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a224aca31f9e8189294f9072ee0fc015a">Dn_output</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr> <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a9f8c0a5b5adedad8f2f3f503cb5510f6">micro_data</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">87</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr> <tr><td colspan="2"><h2><a name="Module Instances"></a> Module Instances</h2></td></tr> <tr><td class="memItemLeft" align="right" valign="top"><b><a class="el" href="classmemory__registers.html#a892186b1bfe856b1ddaf1d8b3a448f50">altsyncram::an_ram_inst</a> </b> </td><td class="memItemRight" valign="bottom"></td></tr> <tr><td class="memItemLeft" align="right" valign="top"><b><a class="el" href="classmemory__registers.html#a5b0f1fb5a259a06899ac6ac3b52835e0">altsyncram::dn_ram_inst</a> </b> </td><td class="memItemRight" valign="bottom"></td></tr> <tr><td class="memItemLeft" align="right" valign="top"><b><a class="el" href="classmemory__registers.html#afc54073a43b749eb1f1376c4b31cd1e3">altsyncram::micro_rom_inst</a> </b> </td><td class="memItemRight" valign="bottom"></td></tr> <tr><td colspan="2"><h2><a name="Signals"></a> Signals</h2></td></tr> <tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classmemory__registers.html#acfe7cd131da7ea586dcb50bea9457678">An_ram_write_enable</a> </td></tr> <tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classmemory__registers.html#a162864c7253e9c74e47b2822eacde9d4">An_ram_output</a> </td></tr> <tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classmemory__registers.html#a3ab032d1bc007200d49892a2ab390732">dn_byteena</a> </td></tr> </table> <hr/><a name="_details"></a><h2>Detailed Description</h2> <p>Contains the microcode ROM and D0-D7, A0-A7 registers. </p> <p>The <a class="el" href="classmemory__registers.html" title="Contains the microcode ROM and D0-D7, A0-A7 registers.">memory_registers</a> module contains:</p> <ul> <li>data and address registers (D0-D7, A0-A7) implemented as an on-chip RAM.</li> <li>the microcode implemented as an on-chip ROM.</li> </ul> <p>Currently this module contains <em>altsyncram</em> instantiations from Altera Megafunction/LPM library. </p> <p>Definition at line <a class="el" href="ao68000_8v_source.html#l02043">2043</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p> <hr/><h2>Member Function Documentation</h2> <a class="anchor" id="a09281e3224878c570c81844785844fe0"></a><!-- doxytag: member="memory_registers::ALWAYS_29" ref="a09281e3224878c570c81844785844fe0" args="clock, reset_n" --> <div class="memitem"> <div class="memproto"> <table class="memname"> <tr> <td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_29 <td></td> <td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classmemory__registers.html#a30d6f9a116a35132d3ae1ac844480c7f">clock</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> , </td> </tr> <tr> <td class="paramkey"></td> <td></td> <td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classmemory__registers.html#a0070367d69af978092b5cd0b60dec77b">reset_n</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> ) </td> </tr> <code> [Always Construct]</code></td> </tr> </table> </div> <div class="memdoc"> <p>Definition at line <a class="el" href="ao68000_8v_source.html#l02076">2076</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p> </div> </div> <hr/><h2>Member Data Documentation</h2> <a class="anchor" id="a30d6f9a116a35132d3ae1ac844480c7f"></a><!-- doxytag: member="memory_registers::clock" ref="a30d6f9a116a35132d3ae1ac844480c7f" args="" --> <div class="memitem"> <div class="memproto"> <table class="memname"> <tr> <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a30d6f9a116a35132d3ae1ac844480c7f">clock</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td> </tr> </table> </div> <div class="memdoc"> <p>Definition at line <a class="el" href="ao68000_8v_source.html#l02044">2044</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p> </div> </div> <a class="anchor" id="a0070367d69af978092b5cd0b60dec77b"></a><!-- doxytag: member="memory_registers::reset_n" ref="a0070367d69af978092b5cd0b60dec77b" args="" --> <div class="memitem"> <div class="memproto"> <table class="memname"> <tr> <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a0070367d69af978092b5cd0b60dec77b">reset_n</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td> </tr> </table> </div> <div class="memdoc"> <p>Definition at line <a class="el" href="ao68000_8v_source.html#l02045">2045</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p> </div> </div> <a class="anchor" id="af3fdc1a826e2d4992fc50550160eed52"></a><!-- doxytag: member="memory_registers::An_address" ref="af3fdc1a826e2d4992fc50550160eed52" args="" --> <div class="memitem"> <div class="memproto"> <table class="memname"> <tr> <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#af3fdc1a826e2d4992fc50550160eed52">An_address</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td> </tr> </table> </div> <div class="memdoc"> <p>Definition at line <a class="el" href="ao68000_8v_source.html#l02048">2048</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p> </div> </div> <a class="anchor" id="a05d2b0cd0706cfcb62674e59ed049b22"></a><!-- doxytag: member="memory_registers::An_input" ref="a05d2b0cd0706cfcb62674e59ed049b22" args="" --> <div class="memitem"> <div class="memproto"> <table class="memname"> <tr> <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a05d2b0cd0706cfcb62674e59ed049b22">An_input</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td> </tr> </table> </div> <div class="memdoc"> <p>Definition at line <a class="el" href="ao68000_8v_source.html#l02049">2049</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p> </div> </div> <a class="anchor" id="abfa12b67b2dfb6da21584304919f0a15"></a><!-- doxytag: member="memory_registers::An_write_enable" ref="abfa12b67b2dfb6da21584304919f0a15" args="" --> <div class="memitem"> <div class="memproto"> <table class="memname"> <tr> <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#abfa12b67b2dfb6da21584304919f0a15">An_write_enable</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td> </tr> </table> </div> <div class="memdoc"> <p>Definition at line <a class="el" href="ao68000_8v_source.html#l02050">2050</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p> </div> </div> <a class="anchor" id="afe969a18dcdd487deeedc9f9146ef8c9"></a><!-- doxytag: member="memory_registers::An_output" ref="afe969a18dcdd487deeedc9f9146ef8c9" args="" --> <div class="memitem"> <div class="memproto"> <table class="memname"> <tr> <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#afe969a18dcdd487deeedc9f9146ef8c9">An_output</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td> </tr> </table> </div> <div class="memdoc"> <p>Definition at line <a class="el" href="ao68000_8v_source.html#l02051">2051</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p> </div> </div> <a class="anchor" id="a3380b9a07ee51a05b97308d5a7257972"></a><!-- doxytag: member="memory_registers::usp" ref="a3380b9a07ee51a05b97308d5a7257972" args="" --> <div class="memitem"> <div class="memproto"> <table class="memname"> <tr> <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a3380b9a07ee51a05b97308d5a7257972">usp</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td> </tr> </table> </div> <div class="memdoc"> <p>Definition at line <a class="el" href="ao68000_8v_source.html#l02053">2053</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p> </div> </div> <a class="anchor" id="a55db549a365e2da7b32c589888f22c1f"></a><!-- doxytag: member="memory_registers::Dn_address" ref="a55db549a365e2da7b32c589888f22c1f" args="" --> <div class="memitem"> <div class="memproto"> <table class="memname"> <tr> <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a55db549a365e2da7b32c589888f22c1f">Dn_address</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td> </tr> </table> </div> <div class="memdoc"> <p>Definition at line <a class="el" href="ao68000_8v_source.html#l02055">2055</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p> </div> </div> <a class="anchor" id="a70e26deed20065da35879d3ce4a7f06e"></a><!-- doxytag: member="memory_registers::Dn_input" ref="a70e26deed20065da35879d3ce4a7f06e" args="" --> <div class="memitem"> <div class="memproto"> <table class="memname"> <tr> <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a70e26deed20065da35879d3ce4a7f06e">Dn_input</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td> </tr> </table> </div> <div class="memdoc"> <p>Definition at line <a class="el" href="ao68000_8v_source.html#l02056">2056</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p> </div> </div> <a class="anchor" id="a515d2e4fc82f04802e46d5eae5d0f0f5"></a><!-- doxytag: member="memory_registers::Dn_write_enable" ref="a515d2e4fc82f04802e46d5eae5d0f0f5" args="" --> <div class="memitem"> <div class="memproto"> <table class="memname"> <tr> <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a515d2e4fc82f04802e46d5eae5d0f0f5">Dn_write_enable</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td> </tr> </table> </div> <div class="memdoc"> <p>Definition at line <a class="el" href="ao68000_8v_source.html#l02057">2057</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p> </div> </div> <a class="anchor" id="a7e475d550020f2ef86841dd171ddf94e"></a><!-- doxytag: member="memory_registers::Dn_size" ref="a7e475d550020f2ef86841dd171ddf94e" args="" --> <div class="memitem"> <div class="memproto"> <table class="memname"> <tr> <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a7e475d550020f2ef86841dd171ddf94e">Dn_size</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">1</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td> </tr> </table> </div> <div class="memdoc"> <p>Definition at line <a class="el" href="ao68000_8v_source.html#l02059">2059</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p> </div> </div> <a class="anchor" id="a224aca31f9e8189294f9072ee0fc015a"></a><!-- doxytag: member="memory_registers::Dn_output" ref="a224aca31f9e8189294f9072ee0fc015a" args="" --> <div class="memitem"> <div class="memproto"> <table class="memname"> <tr> <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a224aca31f9e8189294f9072ee0fc015a">Dn_output</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td> </tr> </table> </div> <div class="memdoc"> <p>Definition at line <a class="el" href="ao68000_8v_source.html#l02060">2060</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p> </div> </div> <a class="anchor" id="a242c22630fbc44df8a129350db77b3d0"></a><!-- doxytag: member="memory_registers::micro_pc" ref="a242c22630fbc44df8a129350db77b3d0" args="" --> <div class="memitem"> <div class="memproto"> <table class="memname"> <tr> <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a242c22630fbc44df8a129350db77b3d0">micro_pc</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">8</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td> </tr> </table> </div> <div class="memdoc"> <p>Definition at line <a class="el" href="ao68000_8v_source.html#l02062">2062</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p> </div> </div> <a class="anchor" id="a9f8c0a5b5adedad8f2f3f503cb5510f6"></a><!-- doxytag: member="memory_registers::micro_data" ref="a9f8c0a5b5adedad8f2f3f503cb5510f6" args="" --> <div class="memitem"> <div class="memproto"> <table class="memname"> <tr> <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a9f8c0a5b5adedad8f2f3f503cb5510f6">micro_data</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">87</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td> </tr> </table> </div> <div class="memdoc"> <p>Definition at line <a class="el" href="ao68000_8v_source.html#l02063">2063</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p> </div> </div> <a class="anchor" id="acfe7cd131da7ea586dcb50bea9457678"></a><!-- doxytag: member="memory_registers::An_ram_write_enable" ref="acfe7cd131da7ea586dcb50bea9457678" args="wire" --> <div class="memitem"> <div class="memproto"> <table class="memname"> <tr> <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#acfe7cd131da7ea586dcb50bea9457678">An_ram_write_enable</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire]</code></td> </tr> </table> </div> <div class="memdoc"> <p>Definition at line <a class="el" href="ao68000_8v_source.html#l02066">2066</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p> </div> </div> <a class="anchor" id="a162864c7253e9c74e47b2822eacde9d4"></a><!-- doxytag: member="memory_registers::An_ram_output" ref="a162864c7253e9c74e47b2822eacde9d4" args="wire[31:0]" --> <div class="memitem"> <div class="memproto"> <table class="memname"> <tr> <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a162864c7253e9c74e47b2822eacde9d4">An_ram_output</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[31:0]]</code></td> </tr> </table> </div> <div class="memdoc"> <p>Definition at line <a class="el" href="ao68000_8v_source.html#l02068">2068</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p> </div> </div> <a class="anchor" id="a3ab032d1bc007200d49892a2ab390732"></a><!-- doxytag: member="memory_registers::dn_byteena" ref="a3ab032d1bc007200d49892a2ab390732" args="wire[3:0]" --> <div class="memitem"> <div class="memproto"> <table class="memname"> <tr> <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a3ab032d1bc007200d49892a2ab390732">dn_byteena</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[3:0]]</code></td> </tr> </table> </div> <div class="memdoc"> <p>Definition at line <a class="el" href="ao68000_8v_source.html#l02071">2071</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p> </div> </div> <a class="anchor" id="a892186b1bfe856b1ddaf1d8b3a448f50"></a><!-- doxytag: member="memory_registers::altsyncram" ref="a892186b1bfe856b1ddaf1d8b3a448f50" args="" --> <div class="memitem"> <div class="memproto"> <table class="memname"> <tr> <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a892186b1bfe856b1ddaf1d8b3a448f50">altsyncram</a></span> <b><span class="vhdlchar">an_ram_inst</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Module Instance]</code></td> </tr> </table> </div> <div class="memdoc"> <p>Definition at line <a class="el" href="ao68000_8v_source.html#l02082">2082</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p> </div> </div> <a class="anchor" id="a5b0f1fb5a259a06899ac6ac3b52835e0"></a><!-- doxytag: member="memory_registers::altsyncram" ref="a5b0f1fb5a259a06899ac6ac3b52835e0" args="" --> <div class="memitem"> <div class="memproto"> <table class="memname"> <tr> <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a5b0f1fb5a259a06899ac6ac3b52835e0">altsyncram</a></span> <b><span class="vhdlchar">dn_ram_inst</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Module Instance]</code></td> </tr> </table> </div> <div class="memdoc"> <p>Definition at line <a class="el" href="ao68000_8v_source.html#l02098">2098</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p> </div> </div> <a class="anchor" id="afc54073a43b749eb1f1376c4b31cd1e3"></a><!-- doxytag: member="memory_registers::altsyncram" ref="afc54073a43b749eb1f1376c4b31cd1e3" args="" --> <div class="memitem"> <div class="memproto"> <table class="memname"> <tr> <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#afc54073a43b749eb1f1376c4b31cd1e3">altsyncram</a></span> <b><span class="vhdlchar">micro_rom_inst</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Module Instance]</code></td> </tr> </table> </div> <div class="memdoc"> <p>Definition at line <a class="el" href="ao68000_8v_source.html#l02114">2114</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p> </div> </div> <hr/>The documentation for this class was generated from the following file:<ul> <li><a class="el" href="ao68000_8v_source.html">ao68000.v</a></li> </ul> </div> <hr class="footer"/><address class="footer"><small>Generated on Mon Dec 20 2010 21:20:20 for aoOCS by  <a href="http://www.doxygen.org/index.html"> <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.2 </small></address> </body> </html>