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<h1>ocs_serial Module Reference</h1> </div>
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<!-- doxytag: class="ocs_serial" -->
<p><p>OCS serial port implementation with WISHBONE slave interface. [functionality not implemented]. </p>
<a href="#_details">More...</a></p>
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Inheritance diagram for ocs_serial:<!-- endSectionHeader --></div>
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<p><a href="classocs__serial-members.html">List of all members.</a></p>
<table class="memberdecls">
<tr><td colspan="2"><h2><a name="Always Constructs"></a>
Always Constructs</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__serial.html#a52fa402c182371c96de65a44f4d0ad27">ALWAYS_49</a> </td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classocs__serial.html#afaf38f6309d65be30657673eda60b0d5">CLK_I</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classocs__serial.html#ab056ba3c82108a98db62cab2629c2f11">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
<tr><td colspan="2"><h2><a name="Inputs"></a>
Inputs</h2></td></tr>
<tr><td colspan="2"><div class="groupHeader">Clock and reset</div></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__serial.html#afaf38f6309d65be30657673eda60b0d5">CLK_I</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__serial.html#ab056ba3c82108a98db62cab2629c2f11">reset_n</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td colspan="2"><div class="groupHeader">WISHBONE slave</div></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__serial.html#a220f1561e548a7d1762e444e0a3a8255">CYC_I</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__serial.html#a71181c2f7c1786e7c8d36efcc5cd6384">STB_I</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__serial.html#a26ba3360a85981afe01b1ba0d42ded79">WE_I</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__serial.html#ab522ee14d28ba506e3257da274de8052">ADR_I</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">8</span><span class="vhdlchar">:</span><span class="vhdldigit">2</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__serial.html#ae600c0f33099d217d6d6590c913a0474">SEL_I</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__serial.html#ae8dce78204888df829f52c2943d646bd">DAT_I</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td colspan="2"><div class="groupHeader">Not aligned register access on a 32-bit WISHBONE bus</div></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__serial.html#a41b01454461979054072a9dd162861fe">na_dskbytr</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">15</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td colspan="2"><h2><a name="Outputs"></a>
Outputs</h2></td></tr>
<tr><td colspan="2"><div class="groupHeader">WISHBONE slave</div></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__serial.html#a845b761bb592b34bbef8610710b4d089">DAT_O</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__serial.html#a469e46a6b2d056ab92f642bd7166a09b">ACK_O</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td colspan="2"><div class="groupHeader">Not aligned register access on a 32-bit WISHBONE bus</div></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__serial.html#a22cfe10bb9f32bd121b3e485129036ad">na_dskbytr_read</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
</table>
<hr/><a name="_details"></a><h2>Detailed Description</h2>
<p>OCS serial port implementation with WISHBONE slave interface. [functionality not implemented]. </p>
<p>List of serial registers: </p>
<div class="fragment"><pre class="fragment">
Not implemented:
SERDATR *018 R P Serial port data and status read read implemented here
[DSKBYTR *01A R P Disk data byte and status read read implemented here]
SERDAT *030 W P Serial port data and stop bits write
SERPER *032 W P Serial port period and control
</pre></div>
<p>Definition at line <a class="el" href="ocs__serial_8v_source.html#l00042">42</a> of file <a class="el" href="ocs__serial_8v_source.html">ocs_serial.v</a>.</p>
<hr/><h2>Member Function Documentation</h2>
<a class="anchor" id="a52fa402c182371c96de65a44f4d0ad27"></a><!-- doxytag: member="ocs_serial::ALWAYS_49" ref="a52fa402c182371c96de65a44f4d0ad27" args="CLK_I, reset_n" -->
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<td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_49 <td></td>
<td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classocs__serial.html#afaf38f6309d65be30657673eda60b0d5">CLK_I</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> , </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classocs__serial.html#ab056ba3c82108a98db62cab2629c2f11">reset_n</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> ) </td>
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<code> [Always Construct]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ocs__serial_8v_source.html#l00072">72</a> of file <a class="el" href="ocs__serial_8v_source.html">ocs_serial.v</a>.</p>
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<hr/><h2>Member Data Documentation</h2>
<a class="anchor" id="afaf38f6309d65be30657673eda60b0d5"></a><!-- doxytag: member="ocs_serial::CLK_I" ref="afaf38f6309d65be30657673eda60b0d5" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classocs__serial.html#afaf38f6309d65be30657673eda60b0d5">CLK_I</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
</tr>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ocs__serial_8v_source.html#l00045">45</a> of file <a class="el" href="ocs__serial_8v_source.html">ocs_serial.v</a>.</p>
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<a class="anchor" id="ab056ba3c82108a98db62cab2629c2f11"></a><!-- doxytag: member="ocs_serial::reset_n" ref="ab056ba3c82108a98db62cab2629c2f11" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classocs__serial.html#ab056ba3c82108a98db62cab2629c2f11">reset_n</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ocs__serial_8v_source.html#l00046">46</a> of file <a class="el" href="ocs__serial_8v_source.html">ocs_serial.v</a>.</p>
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<a class="anchor" id="a220f1561e548a7d1762e444e0a3a8255"></a><!-- doxytag: member="ocs_serial::CYC_I" ref="a220f1561e548a7d1762e444e0a3a8255" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classocs__serial.html#a220f1561e548a7d1762e444e0a3a8255">CYC_I</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
</tr>
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</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="ocs__serial_8v_source.html#l00051">51</a> of file <a class="el" href="ocs__serial_8v_source.html">ocs_serial.v</a>.</p>
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<a class="anchor" id="a71181c2f7c1786e7c8d36efcc5cd6384"></a><!-- doxytag: member="ocs_serial::STB_I" ref="a71181c2f7c1786e7c8d36efcc5cd6384" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classocs__serial.html#a71181c2f7c1786e7c8d36efcc5cd6384">STB_I</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ocs__serial_8v_source.html#l00052">52</a> of file <a class="el" href="ocs__serial_8v_source.html">ocs_serial.v</a>.</p>
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<a class="anchor" id="a26ba3360a85981afe01b1ba0d42ded79"></a><!-- doxytag: member="ocs_serial::WE_I" ref="a26ba3360a85981afe01b1ba0d42ded79" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classocs__serial.html#a26ba3360a85981afe01b1ba0d42ded79">WE_I</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ocs__serial_8v_source.html#l00053">53</a> of file <a class="el" href="ocs__serial_8v_source.html">ocs_serial.v</a>.</p>
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<a class="anchor" id="ab522ee14d28ba506e3257da274de8052"></a><!-- doxytag: member="ocs_serial::ADR_I" ref="ab522ee14d28ba506e3257da274de8052" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classocs__serial.html#ab522ee14d28ba506e3257da274de8052">ADR_I</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">8</span><span class="vhdlchar">:</span><span class="vhdldigit">2</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ocs__serial_8v_source.html#l00054">54</a> of file <a class="el" href="ocs__serial_8v_source.html">ocs_serial.v</a>.</p>
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<a class="anchor" id="ae600c0f33099d217d6d6590c913a0474"></a><!-- doxytag: member="ocs_serial::SEL_I" ref="ae600c0f33099d217d6d6590c913a0474" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classocs__serial.html#ae600c0f33099d217d6d6590c913a0474">SEL_I</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ocs__serial_8v_source.html#l00055">55</a> of file <a class="el" href="ocs__serial_8v_source.html">ocs_serial.v</a>.</p>
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<a class="anchor" id="ae8dce78204888df829f52c2943d646bd"></a><!-- doxytag: member="ocs_serial::DAT_I" ref="ae8dce78204888df829f52c2943d646bd" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classocs__serial.html#ae8dce78204888df829f52c2943d646bd">DAT_I</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ocs__serial_8v_source.html#l00056">56</a> of file <a class="el" href="ocs__serial_8v_source.html">ocs_serial.v</a>.</p>
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<a class="anchor" id="a845b761bb592b34bbef8610710b4d089"></a><!-- doxytag: member="ocs_serial::DAT_O" ref="a845b761bb592b34bbef8610710b4d089" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classocs__serial.html#a845b761bb592b34bbef8610710b4d089">DAT_O</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ocs__serial_8v_source.html#l00057">57</a> of file <a class="el" href="ocs__serial_8v_source.html">ocs_serial.v</a>.</p>
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<a class="anchor" id="a469e46a6b2d056ab92f642bd7166a09b"></a><!-- doxytag: member="ocs_serial::ACK_O" ref="a469e46a6b2d056ab92f642bd7166a09b" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classocs__serial.html#a469e46a6b2d056ab92f642bd7166a09b">ACK_O</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ocs__serial_8v_source.html#l00058">58</a> of file <a class="el" href="ocs__serial_8v_source.html">ocs_serial.v</a>.</p>
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<a class="anchor" id="a22cfe10bb9f32bd121b3e485129036ad"></a><!-- doxytag: member="ocs_serial::na_dskbytr_read" ref="a22cfe10bb9f32bd121b3e485129036ad" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classocs__serial.html#a22cfe10bb9f32bd121b3e485129036ad">na_dskbytr_read</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ocs__serial_8v_source.html#l00064">64</a> of file <a class="el" href="ocs__serial_8v_source.html">ocs_serial.v</a>.</p>
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<a class="anchor" id="a41b01454461979054072a9dd162861fe"></a><!-- doxytag: member="ocs_serial::na_dskbytr" ref="a41b01454461979054072a9dd162861fe" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classocs__serial.html#a41b01454461979054072a9dd162861fe">na_dskbytr</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">15</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ocs__serial_8v_source.html#l00065">65</a> of file <a class="el" href="ocs__serial_8v_source.html">ocs_serial.v</a>.</p>
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<hr/>The documentation for this class was generated from the following file:<ul>
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