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<h1>ocs_serial.v</h1> </div>
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<a href="ocs__serial_8v.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="keyword">/*</span>
<a name="l00002"></a>00002 <span class="keyword"> Copyright 2010, Aleksander Osman, alfik@poczta.fm. All rights reserved.</span>
<a name="l00003"></a>00003 <span class="keyword"> </span>
<a name="l00004"></a>00004 <span class="keyword"> Redistribution and use in source and binary forms, with or without modification, are</span>
<a name="l00005"></a>00005 <span class="keyword"> permitted provided that the following conditions are met:</span>
<a name="l00006"></a>00006 <span class="keyword"> </span>
<a name="l00007"></a>00007 <span class="keyword"> 1. Redistributions of source code must retain the above copyright notice, this list of</span>
<a name="l00008"></a>00008 <span class="keyword"> conditions and the following disclaimer.</span>
<a name="l00009"></a>00009 <span class="keyword"> </span>
<a name="l00010"></a>00010 <span class="keyword"> 2. Redistributions in binary form must reproduce the above copyright notice, this list</span>
<a name="l00011"></a>00011 <span class="keyword"> of conditions and the following disclaimer in the documentation and/or other materials</span>
<a name="l00012"></a>00012 <span class="keyword"> provided with the distribution.</span>
<a name="l00013"></a>00013 <span class="keyword"> </span>
<a name="l00014"></a>00014 <span class="keyword"> THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED</span>
<a name="l00015"></a>00015 <span class="keyword"> WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND</span>
<a name="l00016"></a>00016 <span class="keyword"> FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR</span>
<a name="l00017"></a>00017 <span class="keyword"> CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR</span>
<a name="l00018"></a>00018 <span class="keyword"> CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR</span>
<a name="l00019"></a>00019 <span class="keyword"> SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON</span>
<a name="l00020"></a>00020 <span class="keyword"> ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING</span>
<a name="l00021"></a>00021 <span class="keyword"> NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF</span>
<a name="l00022"></a>00022 <span class="keyword"> ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</span>
<a name="l00023"></a>00023 <span class="keyword"> */</span>
<a name="l00024"></a>00024
<a name="l00025"></a>00025 <span class="keyword">/*! \file</span>
<a name="l00026"></a>00026 <span class="keyword"> \brief OCS serial port implementation with WISHBONE slave interface. [functionality not implemented]</span>
<a name="l00027"></a>00027 <span class="keyword"> */</span>
<a name="l00028"></a>00028
<a name="l00029"></a>00029 <span class="keyword">/*! \brief \copybrief ocs_serial.v</span>
<a name="l00030"></a>00030 <span class="keyword"></span>
<a name="l00031"></a>00031 <span class="keyword">List of serial registers:</span>
<a name="l00032"></a>00032 <span class="keyword">\verbatim</span>
<a name="l00033"></a>00033 <span class="keyword">Not implemented:</span>
<a name="l00034"></a>00034 <span class="keyword"> SERDATR *018 R P Serial port data and status read read implemented here</span>
<a name="l00035"></a>00035 <span class="keyword"> [DSKBYTR *01A R P Disk data byte and status read read implemented here]</span>
<a name="l00036"></a>00036 <span class="keyword"></span>
<a name="l00037"></a>00037 <span class="keyword"> SERDAT *030 W P Serial port data and stop bits write</span>
<a name="l00038"></a>00038 <span class="keyword"> SERPER *032 W P Serial port period and control</span>
<a name="l00039"></a>00039 <span class="keyword">\endverbatim</span>
<a name="l00040"></a>00040 <span class="keyword">*/</span>
<a name="l00041"></a>00041
<a name="l00042"></a><a class="code" href="classocs__serial.html">00042</a> <span class="vhdlkeyword">module</span> <a class="code" href="classocs__serial.html">ocs_serial</a>(
<a name="l00043"></a>00043 <span class="keyword">//% \name Clock and reset
</span>
<a name="l00044"></a>00044 <span class="keyword">//% @{</span>
<a name="l00045"></a><a class="code" href="classocs__serial.html#afaf38f6309d65be30657673eda60b0d5">00045</a> <span class="vhdlkeyword">input</span> <a class="code" href="classocs__serial.html#afaf38f6309d65be30657673eda60b0d5">CLK_I</a>,
<a name="l00046"></a><a class="code" href="classocs__serial.html#ab056ba3c82108a98db62cab2629c2f11">00046</a> <span class="vhdlkeyword">input</span> <a class="code" href="classocs__serial.html#ab056ba3c82108a98db62cab2629c2f11">reset_n</a>,
<a name="l00047"></a>00047 <span class="keyword">//% @}</span>
<a name="l00048"></a>00048
<a name="l00049"></a>00049 <span class="keyword">//% \name WISHBONE slave
</span>
<a name="l00050"></a>00050 <span class="keyword">//% @{</span>
<a name="l00051"></a><a class="code" href="classocs__serial.html#a220f1561e548a7d1762e444e0a3a8255">00051</a> <span class="vhdlkeyword">input</span> <a class="code" href="classocs__serial.html#a220f1561e548a7d1762e444e0a3a8255">CYC_I</a>,
<a name="l00052"></a><a class="code" href="classocs__serial.html#a71181c2f7c1786e7c8d36efcc5cd6384">00052</a> <span class="vhdlkeyword">input</span> <a class="code" href="classocs__serial.html#a71181c2f7c1786e7c8d36efcc5cd6384">STB_I</a>,
<a name="l00053"></a><a class="code" href="classocs__serial.html#a26ba3360a85981afe01b1ba0d42ded79">00053</a> <span class="vhdlkeyword">input</span> <a class="code" href="classocs__serial.html#a26ba3360a85981afe01b1ba0d42ded79">WE_I</a>,
<a name="l00054"></a><a class="code" href="classocs__serial.html#ab522ee14d28ba506e3257da274de8052">00054</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">2</span>] <a class="code" href="classocs__serial.html#ab522ee14d28ba506e3257da274de8052">ADR_I</a>,
<a name="l00055"></a><a class="code" href="classocs__serial.html#ae600c0f33099d217d6d6590c913a0474">00055</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] <a class="code" href="classocs__serial.html#ae600c0f33099d217d6d6590c913a0474">SEL_I</a>,
<a name="l00056"></a><a class="code" href="classocs__serial.html#ae8dce78204888df829f52c2943d646bd">00056</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classocs__serial.html#ae8dce78204888df829f52c2943d646bd">DAT_I</a>,
<a name="l00057"></a><a class="code" href="classocs__serial.html#a845b761bb592b34bbef8610710b4d089">00057</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classocs__serial.html#a845b761bb592b34bbef8610710b4d089">DAT_O</a>,
<a name="l00058"></a><a class="code" href="classocs__serial.html#a469e46a6b2d056ab92f642bd7166a09b">00058</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> <a class="code" href="classocs__serial.html#a469e46a6b2d056ab92f642bd7166a09b">ACK_O</a>,
<a name="l00059"></a>00059 <span class="keyword">//% @}</span>
<a name="l00060"></a>00060
<a name="l00061"></a>00061 <span class="keyword">//% \name Not aligned register access on a 32-bit WISHBONE bus
</span>
<a name="l00062"></a>00062 <span class="keyword">//% @{</span>
<a name="l00063"></a>00063 <span class="keyword">// DSKBYTR read implemented here</span>
<a name="l00064"></a><a class="code" href="classocs__serial.html#a22cfe10bb9f32bd121b3e485129036ad">00064</a> <span class="vhdlkeyword">output</span> <a class="code" href="classocs__serial.html#a22cfe10bb9f32bd121b3e485129036ad">na_dskbytr_read</a>,
<a name="l00065"></a><a class="code" href="classocs__serial.html#a41b01454461979054072a9dd162861fe">00065</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] <a class="code" href="classocs__serial.html#a41b01454461979054072a9dd162861fe">na_dskbytr</a>
<a name="l00066"></a>00066 <span class="keyword">//% @}</span>
<a name="l00067"></a>00067 );
<a name="l00068"></a>00068
<a name="l00069"></a>00069 <span class="vhdlkeyword">assign</span> <a class="code" href="classocs__serial.html#a22cfe10bb9f32bd121b3e485129036ad">na_dskbytr_read</a> =
<a name="l00070"></a>00070 (<a class="code" href="classocs__serial.html#a220f1561e548a7d1762e444e0a3a8255">CYC_I</a> == <span class="vhdllogic">1'b1</span> && <a class="code" href="classocs__serial.html#a71181c2f7c1786e7c8d36efcc5cd6384">STB_I</a> == <span class="vhdllogic">1'b1</span> && <a class="code" href="classocs__serial.html#a26ba3360a85981afe01b1ba0d42ded79">WE_I</a> == <span class="vhdllogic">1'b0</span> && { <a class="code" href="classocs__serial.html#ab522ee14d28ba506e3257da274de8052">ADR_I</a>, <span class="vhdllogic">2'b0</span> } == <span class="vhdllogic">9'h018</span> && <a class="code" href="classocs__serial.html#ae600c0f33099d217d6d6590c913a0474">SEL_I</a>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] != <span class="vhdllogic">2'b00</span> && <a class="code" href="classocs__serial.html#a469e46a6b2d056ab92f642bd7166a09b">ACK_O</a> == <span class="vhdllogic">1'b0</span>);
<a name="l00071"></a>00071
<a name="l00072"></a><a class="code" href="classocs__serial.html#a52fa402c182371c96de65a44f4d0ad27">00072</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classocs__serial.html#afaf38f6309d65be30657673eda60b0d5">CLK_I</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classocs__serial.html#ab056ba3c82108a98db62cab2629c2f11">reset_n</a>) <span class="vhdlkeyword">begin</span>
<a name="l00073"></a>00073 <span class="vhdlkeyword">if</span>(<a class="code" href="classocs__serial.html#ab056ba3c82108a98db62cab2629c2f11">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
<a name="l00074"></a>00074 <a class="code" href="classocs__serial.html#a845b761bb592b34bbef8610710b4d089">DAT_O</a> <= <span class="vhdllogic">32'd0</span>;
<a name="l00075"></a>00075 <a class="code" href="classocs__serial.html#a469e46a6b2d056ab92f642bd7166a09b">ACK_O</a> <= <span class="vhdllogic">1'b0</span>;
<a name="l00076"></a>00076 <span class="vhdlkeyword">end</span>
<a name="l00077"></a>00077 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
<a name="l00078"></a>00078 <span class="vhdlkeyword">if</span>(<a class="code" href="classocs__serial.html#a220f1561e548a7d1762e444e0a3a8255">CYC_I</a> == <span class="vhdllogic">1'b1</span> && <a class="code" href="classocs__serial.html#a71181c2f7c1786e7c8d36efcc5cd6384">STB_I</a> == <span class="vhdllogic">1'b1</span> && <a class="code" href="classocs__serial.html#a469e46a6b2d056ab92f642bd7166a09b">ACK_O</a> == <span class="vhdllogic">1'b0</span>) <a class="code" href="classocs__serial.html#a469e46a6b2d056ab92f642bd7166a09b">ACK_O</a> <= <span class="vhdllogic">1'b1</span>;
<a name="l00079"></a>00079 <span class="vhdlkeyword">else</span> <a class="code" href="classocs__serial.html#a469e46a6b2d056ab92f642bd7166a09b">ACK_O</a> <= <span class="vhdllogic">1'b0</span>;
<a name="l00080"></a>00080
<a name="l00081"></a>00081 <span class="vhdlkeyword">if</span>(<a class="code" href="classocs__serial.html#a220f1561e548a7d1762e444e0a3a8255">CYC_I</a> == <span class="vhdllogic">1'b1</span> && <a class="code" href="classocs__serial.html#a71181c2f7c1786e7c8d36efcc5cd6384">STB_I</a> == <span class="vhdllogic">1'b1</span> && <a class="code" href="classocs__serial.html#a26ba3360a85981afe01b1ba0d42ded79">WE_I</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
<a name="l00082"></a>00082 <span class="vhdlkeyword">if</span>({ <a class="code" href="classocs__serial.html#ab522ee14d28ba506e3257da274de8052">ADR_I</a>, <span class="vhdllogic">2'b0</span> } == <span class="vhdllogic">9'h018</span> && <a class="code" href="classocs__serial.html#ae600c0f33099d217d6d6590c913a0474">SEL_I</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classocs__serial.html#a845b761bb592b34bbef8610710b4d089">DAT_O</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classocs__serial.html#a41b01454461979054072a9dd162861fe">na_dskbytr</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
<a name="l00083"></a>00083 <span class="vhdlkeyword">if</span>({ <a class="code" href="classocs__serial.html#ab522ee14d28ba506e3257da274de8052">ADR_I</a>, <span class="vhdllogic">2'b0</span> } == <span class="vhdllogic">9'h018</span> && <a class="code" href="classocs__serial.html#ae600c0f33099d217d6d6590c913a0474">SEL_I</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classocs__serial.html#a845b761bb592b34bbef8610710b4d089">DAT_O</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">8</span>] <= <a class="code" href="classocs__serial.html#a41b01454461979054072a9dd162861fe">na_dskbytr</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">8</span>];
<a name="l00084"></a>00084 <span class="vhdlkeyword">if</span>({ <a class="code" href="classocs__serial.html#ab522ee14d28ba506e3257da274de8052">ADR_I</a>, <span class="vhdllogic">2'b0</span> } == <span class="vhdllogic">9'h018</span> && <a class="code" href="classocs__serial.html#ae600c0f33099d217d6d6590c913a0474">SEL_I</a>[<span class="vhdllogic">2</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classocs__serial.html#a845b761bb592b34bbef8610710b4d089">DAT_O</a>[<span class="vhdllogic">23</span>:<span class="vhdllogic">16</span>] <= <span class="vhdllogic">8'd0</span>;
<a name="l00085"></a>00085 <span class="vhdlkeyword">if</span>({ <a class="code" href="classocs__serial.html#ab522ee14d28ba506e3257da274de8052">ADR_I</a>, <span class="vhdllogic">2'b0</span> } == <span class="vhdllogic">9'h018</span> && <a class="code" href="classocs__serial.html#ae600c0f33099d217d6d6590c913a0474">SEL_I</a>[<span class="vhdllogic">3</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classocs__serial.html#a845b761bb592b34bbef8610710b4d089">DAT_O</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">24</span>] <= <span class="vhdllogic">8'd0</span>;
<a name="l00086"></a>00086 <span class="vhdlkeyword">end</span>
<a name="l00087"></a>00087 <span class="vhdlkeyword">end</span>
<a name="l00088"></a>00088 <span class="vhdlkeyword">end</span>
<a name="l00089"></a>00089
<a name="l00090"></a>00090 <span class="vhdlkeyword">endmodule</span>
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