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<h1>Introduction </h1> </div>
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<div class="contents">
<p>The OpenCores <a class="el" href="classaoOCS.html" title="aoOCS top-level module for the Terasic DE2-70 board. ">aoOCS</a> SoC is a Wishbone compatible implementation of most of the Amiga Original Chip Set (OCS) and computer functionality.</p>
<p><a class="el" href="classaoOCS.html" title="aoOCS top-level module for the Terasic DE2-70 board. ">aoOCS</a> is not related in any way with Minimig - it is a new and independent Amiga OCS implementation.</p>
<h3>Features</h3>
<ul>
<li>The <a class="el" href="classaoOCS.html" title="aoOCS top-level module for the Terasic DE2-70 board. ">aoOCS</a> SoC contains the following Amiga/OCS components:<ul>
<li>blitter</li>
<li>copper</li>
<li>system control (interrupts)</li>
<li>video: bitplains, sprites, collision detection</li>
<li>audio: 4 channels, low-pass filter</li>
<li>user input: PS/2 mouse, PS/2 keyboard and joystick (keyboard arrow keys)</li>
<li>floppy: read and write ADF files directly from a SD card. Only the internal floppy drive is implemented</li>
<li>8520 CIA</li>
<li><a class="el" href="classao68000.html" title="ao68000 top level module.">ao68000</a> OpenCores IP core is used as the <a class="el" href="classaoOCS.html" title="aoOCS top-level module for the Terasic DE2-70 board. ">aoOCS</a> processor</li>
</ul>
</li>
<li>All of the above components are WISHBONE revision B.3 compatible</li>
<li>The <a class="el" href="classaoOCS.html" title="aoOCS top-level module for the Terasic DE2-70 board. ">aoOCS</a> contains the following additional components:<ul>
<li>SD card controller written in HDL with DMA. Supports SDHC cards only.</li>
<li>10/100 Mbit Ethernet controller written in HDL to send the current VGA frames (frame grabber)</li>
<li>HDL drivers for SSRAM, PS/2 keyboard, PS/2 mouse, audio codec, VGA DAC</li>
</ul>
</li>
<li><a class="el" href="classaoOCS.html" title="aoOCS top-level module for the Terasic DE2-70 board. ">aoOCS</a> uses only one external memory: a SSRAM with 36-bit words and pipelined access. A video buffer with about 250KB is located SSRAM. Another 256KB are used by the ROM. All the rest memory can be used as Chip RAM.</li>
<li>The On-Screen-Display is implemented in HDL as a finite state machine. No additional controller/processor with firmware required to handle the SoC.</li>
<li>The following options are available on the On-Screen-Display:<ul>
<li>select ROM file to load (only Amiga Kickstart v1.2 was tested)</li>
<li>enable or disable Joystick (keyboard arrow keys)</li>
<li>enable or disable floppy write protection</li>
<li>insert a floppy - select one from a list</li>
<li>eject an inserted floppy</li>
<li>reset the system</li>
</ul>
</li>
<li>The On-Screen-Display is independent of the running Amiga software. It is enabled and disabled by the Home key and controled by the keyboard arrow keys and the right CTRL key.</li>
<li>Only PAL timings are implemented.</li>
<li>The video output is VGA compatible: 640x480 at 70 Hz. A rather simple method is used to extend the 256 PAL horizontal lines to 480 VGA lines: all lines are doubled except for every 8th one.</li>
<li>The system uses generally a single clock: 30 MHz. There are two more clocks: 12 MHz, 25 MHz generated to interface with external hardware (Audio codec, Ethernet controller). A single altpll is used to generate all three clocks from one 50 MHz external clock. More information about clocks is available at <a class="el" href="page_spec_clocks.html">Clocks</a>.</li>
<li>A VGA frame grabber is implemented that sends captured frames by 100 Mbit Ethernet in IP/UDP packets.</li>
<li>The system uses about 26.400 LE on Altera Cyclone II and about 267.000 bits of on-chip RAM.</li>
<li>The blitter functionality was tested against the E-UAE Amiga software emulator.</li>
<li>Tested only on a Terasic DE2-70 board (www.terasic.com.tw).</li>
<li>Documentation generated by Doxygen (www.doxygen.org) with doxverilog patch (<a href="http://developer.berlios.de/projects/doxverilog/">http://developer.berlios.de/projects/doxverilog/</a>). The specification is automatically extracted from the Doxygen HTML output.</li>
</ul>
<h3>WISHBONE compatibility</h3>
<ul>
<li>Version: WISHBONE specification Revision B.3,</li>
<li>General description: 32-bit WISHBONE interface,</li>
<li>WISHBONE data port size: 32-bit,</li>
<li>Data port granularity: 8-bits,</li>
<li>Data port maximum operand size: 32-bits,</li>
<li>Data transfer ordering: BIG ENDIAN,</li>
<li>Data transfer sequencing: UNDEFINED,</li>
<li>Constraints on <code>CLK_I</code> signal: described in <a class="el" href="page_spec_clocks.html">Clocks</a>.</li>
</ul>
<h3>Similar projects</h3>
<p>Other Open-Source Amiga implementations include:</p>
<ul>
<li>Minimig (<a href="http://code.google.com/p/minimig/">http://code.google.com/p/minimig/</a>) - FPGA-based re-implementation of the original Amiga 500 hardware. Runs on the Minimig PCB and also on Terasic DE1,2 boards.</li>
</ul>
<h3>Limitations</h3>
<ul>
<li>No filesystem support on the SD card. Data is read from fixed positions. The contents of the SD card is generated by the <code>aoOCS_tool</code> described at <a class="el" href="page_spec_operation.html">Operation</a>.</li>
<li>No video external synchronize, lace mode, lightpen, genlock audio enable, color composite (BPLCON0)</li>
<li>All bitplain data is fetched at once in a burst memory read at the begining of each line. No changes to the bitplain data done after the beginning of a line are visible.</li>
<li>Currently <a class="el" href="classaoOCS.html" title="aoOCS top-level module for the Terasic DE2-70 board. ">aoOCS</a> requires an 36-bit word SSRAM to store the video buffer. This way 3 pixels 12-bits each can be stored in one word.</li>
<li>Serial port not implemented.</li>
<li>Parallel port not implemented.</li>
<li>Low-pass filter disable/enable by CIA-A port A bit 1 not implemented.</li>
<li>Proportional controller and light pen not implemented.</li>
<li>Some rarely used OCS registers are not implemented: strobe video sync, write beam position, coprocessor instruction fetch identify. For a complete list of not implemented registers look at <a class="el" href="page_spec_registers.html">Registers</a>.</li>
<li>Only some of the Amiga software was tested and works on the <a class="el" href="classaoOCS.html" title="aoOCS top-level module for the Terasic DE2-70 board. ">aoOCS</a>. A list of <a class="el" href="classaoOCS.html" title="aoOCS top-level module for the Terasic DE2-70 board. ">aoOCS</a> software compatability is located at <a class="el" href="page_spec_operation.html">Operation</a>.</li>
</ul>
<h3>TODO</h3>
<ul>
<li>Fix some of the above limitations.</li>
<li>Optimize the design.</li>
<li>Run WISHBONE verification models.</li>
<li>More documentation of Verilog sources.</li>
<li>Describe testing and changes done in E-UAE sources.</li>
<li>Prepare scripts for VATS: run_sim -r -> regresion test.</li>
<li>Port the <a class="el" href="classaoOCS.html" title="aoOCS top-level module for the Terasic DE2-70 board. ">aoOCS</a> SoC to a Xilinx FPGA.</li>
</ul>
<h3>Status</h3>
<ul>
<li>Amiga Workbench v1.2 runs with some minor graphic problems: bottom of screen not displayed correctly.</li>
<li>Prince of Persia runs perfectly.</li>
<li>Wings of Fury runs correctly. Some sound glitches in intro.</li>
<li>Lotus 2 runs correctly. Some sound problems in intro.</li>
<li>Warzone runs poor. Some major graphic problems.</li>
<li>More information about <a class="el" href="classaoOCS.html" title="aoOCS top-level module for the Terasic DE2-70 board. ">aoOCS</a> software compatability is available at <a class="el" href="page_spec_operation.html">Operation</a>.</li>
</ul>
<h3>Requirements</h3>
<ul>
<li>Altera Quartus II synthesis tool (<a href="http://www.altera.com">http://www.altera.com</a>) is required to synthesise the <code><a class="el" href="classaoOCS.html" title="aoOCS top-level module for the Terasic DE2-70 board. ">aoOCS</a></code> System-on-Chip.</li>
<li>Java SDK (<a href="http://java.sun.com">http://java.sun.com</a>) is required to compile the <code>aoOCS_tool</code> (The tool is described in <a class="el" href="page_spec_operation.html">Operation</a>).</li>
<li>A FPGA board. Currently only the Terasic DE2-70 board was tested.</li>
<li>Icarus Verilog simulator (<a href="http://www.icarus.com/eda/verilog/">http://www.icarus.com/eda/verilog/</a>) is required to compile the and run some tests.</li>
<li>Access to Altera Quartus II directory (directory eda/sim_lib/) is required to compile and run some tests.</li>
<li>GCC (<a href="http://gcc.gnu.org">http://gcc.gnu.org</a>) is required to compile some testes based on E-UAE sources. </li>
</ul>
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