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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2010 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 10.0 Build 218 06/27/2010 SJ Web Edition
# Date created = 23:00:23  November 02, 2010
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#               audio_test_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#               assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus II software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C70F896C6
set_global_assignment -name TOP_LEVEL_ENTITY audio_test
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 10.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:00:23  NOVEMBER 02, 2010"
set_global_assignment -name LAST_QUARTUS_VERSION 10.0
set_global_assignment -name VERILOG_FILE audio_test.v
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"

set_location_assignment PIN_J18 -to ac_sclk
set_location_assignment PIN_H18 -to ac_sdat
set_location_assignment PIN_D17 -to ac_xclk
set_location_assignment PIN_E17 -to ac_bclk
set_location_assignment PIN_F18 -to ac_dat
set_location_assignment PIN_G18 -to ac_lr
set_location_assignment PIN_R3 -to clk_50
set_location_assignment PIN_AA23 -to reset_ext_n
set_location_assignment PIN_AC13 -to pc_debug[0]
set_location_assignment PIN_AB13 -to pc_debug[1]
set_location_assignment PIN_AC12 -to pc_debug[2]
set_location_assignment PIN_AB12 -to pc_debug[3]
set_location_assignment PIN_AC11 -to pc_debug[4]
set_location_assignment PIN_AD9 -to pc_debug[5]
set_location_assignment PIN_AD8 -to pc_debug[6]
set_location_assignment PIN_AJ7 -to pc_debug[7]

set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top