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[/] [artec_dongle_ii_fpga/] [tags/] [google_release_of_0x20_firmware/] [src/] [postcode_ser/] [fifo_waveforms.html] - Rev 3
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<html> <head> <title>Sample Waveforms for fifo.vhd </title> </head> <body> <h2><CENTER>Sample behavioral waveforms for design file fifo.vhd </CENTER></h2> <P>The following waveforms show the behavior of scfifo megafunction for the chosen set of parameters in design fifo.vhd. The design fifo.vhd has a depth of 8192 words of 8 bits each. The output of the fifo is registered. The fifo is in legacy synchronous mode. The data becomes available after 'rdreq' is asserted; 'rdreq' acts as a read request. </P> <CENTER><img src=fifo_wave0.jpg> </CENTER> <P><CENTER><FONT size=2>Fig. 1 : Wave showing read and write operation. </CENTER></P> <P><FONT size=3>The above waveform shows the behavior of the design under normal read and write conditions with aclr . </P> <P></P> </body> </html>
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