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[/] [avr_hp/] [trunk/] [ise/] [ise_s3/] [avr_core.twr] - Rev 2
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--------------------------------------------------------------------------------
Release 11.1 Trace (nt)
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
C:\Xilinx\11.1\ISE\bin\nt\unwrapped\trce.exe -ise
C:/EDAptability/coremultiplier/reference/avr/ise/ise_s3/ise_s3/ise_s3.ise
-intstyle ise -v 3 -s 4 -fastpaths -xml avr_core.twx avr_core.ncd -o
avr_core.twr avr_core.pcf -ucf avr_core.ucf
Design file: avr_core.ncd
Physical constraint file: avr_core.pcf
Device,package,speed: xc3s200a,fg320,-4 (PRODUCTION 1.41 2009-03-03)
Report level: verbose report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
================================================================================
Timing constraint: TS_cp2 = PERIOD TIMEGRP "cp2" 24 ns HIGH 50%;
128661977 paths analyzed, 1314 endpoints analyzed, 47 failing endpoints
47 timing errors detected. (47 setup errors, 0 hold errors, 0 component switching limit errors)
Minimum period is 24.997ns.
--------------------------------------------------------------------------------
Slack (setup path): -0.997ns (requirement - (data path - clock path skew + uncertainty))
Source: pm_fetch_dec_Inst/nirq_st0 (FF)
Destination: pm_fetch_dec_Inst/pc_high_5 (FF)
Requirement: 24.000ns
Data Path Delay: 24.914ns (Levels of Logic = 16)
Clock Path Skew: -0.083ns (0.588 - 0.671)
Source Clock: cp2_BUFGP rising at 0.000ns
Destination Clock: cp2_BUFGP rising at 24.000ns
Clock Uncertainty: 0.000ns
Maximum Data Path: pm_fetch_dec_Inst/nirq_st0 to pm_fetch_dec_Inst/pc_high_5
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X6Y29.XQ Tcko 0.631 pm_fetch_dec_Inst/nirq_st0
pm_fetch_dec_Inst/nirq_st0
SLICE_X9Y35.F2 net (fanout=6) 0.828 pm_fetch_dec_Inst/nirq_st0
SLICE_X9Y35.COUT Topcyf 1.195 pm_fetch_dec_Inst/nop_insert_st_wg_cy<1>
pm_fetch_dec_Inst/nop_insert_st_wg_lut<0>
pm_fetch_dec_Inst/nop_insert_st_wg_cy<0>
pm_fetch_dec_Inst/nop_insert_st_wg_cy<1>
SLICE_X9Y36.CIN net (fanout=1) 0.000 pm_fetch_dec_Inst/nop_insert_st_wg_cy<1>
SLICE_X9Y36.COUT Tbyp 0.130 pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>
pm_fetch_dec_Inst/nop_insert_st_wg_cy<2>
pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>
SLICE_X9Y28.G3 net (fanout=13) 1.062 pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>
SLICE_X9Y28.Y Tilo 0.648 pm_fetch_dec_Inst/alu_data_r_in_or0001
pm_fetch_dec_Inst/nop_insert_st_wg_cy<5>1
SLICE_X13Y26.G3 net (fanout=101) 0.773 pm_fetch_dec_Inst/nop_insert_st
SLICE_X13Y26.Y Tilo 0.648 N556
pm_fetch_dec_Inst/reg_rd_adr<3>2
SLICE_X18Y26.G2 net (fanout=3) 0.752 pm_fetch_dec_Inst/reg_rd_adr<3>2
SLICE_X18Y26.Y Tilo 0.707 GPRF_Inst/N188
pm_fetch_dec_Inst/reg_rd_adr<3>47_1
SLICE_X16Y28.G4 net (fanout=14) 0.736 pm_fetch_dec_Inst/reg_rd_adr<3>47
SLICE_X16Y28.Y Tilo 0.707 N603
pm_fetch_dec_Inst/reg_rd_adr<2>62_SW1
SLICE_X17Y28.F1 net (fanout=1) 0.173 N843
SLICE_X17Y28.X Tilo 0.643 GPRF_Inst/N158
GPRF_Inst/sg_tmp_rd_data_31<0>1131
SLICE_X26Y21.F4 net (fanout=7) 1.335 GPRF_Inst/N158
SLICE_X26Y21.X Tilo 0.692 GPRF_Inst/sg_tmp_rd_data_31<2>150
GPRF_Inst/sg_tmp_rd_data_31<2>150
SLICE_X23Y24.F3 net (fanout=1) 0.562 GPRF_Inst/sg_tmp_rd_data_31<2>150
SLICE_X23Y24.X Tilo 0.643 GPRF_Inst/sg_tmp_rd_data_31<2>256
GPRF_Inst/sg_tmp_rd_data_31<2>256
SLICE_X20Y20.G2 net (fanout=2) 0.648 GPRF_Inst/sg_tmp_rd_data_31<2>256
SLICE_X20Y20.Y Tilo 0.707 ALU_Inst/incdec_op_carry<2>
GPRF_Inst/sg_tmp_rd_data_31<2>282_1
SLICE_X19Y31.F3 net (fanout=10) 1.134 GPRF_Inst/sg_tmp_rd_data_31<2>282
SLICE_X19Y31.X Tif5x 0.924 BP_Inst/bit_test_mux_out_7_mux0000184
BP_Inst/bit_test_mux_out_7_mux0000184_G
BP_Inst/bit_test_mux_out_7_mux0000184
SLICE_X6Y44.F2 net (fanout=2) 1.049 BP_Inst/bit_test_mux_out_7_mux0000184
SLICE_X6Y44.X Tilo 0.692 BP_Inst/N01
BP_Inst/bit_test_mux_out_7_mux00001112
SLICE_X4Y57.G4 net (fanout=9) 1.529 BP_Inst/N01
SLICE_X4Y57.Y Tilo 0.707 pm_fetch_dec_Inst/N2
pm_fetch_dec_Inst/brxx_st_and000011
SLICE_X8Y41.F2 net (fanout=13) 1.111 pm_fetch_dec_Inst/cpu_busy_and0000
SLICE_X8Y41.X Tilo 0.692 pm_fetch_dec_Inst/brxx_st
pm_fetch_dec_Inst/I65_mux0000<0>41
SLICE_X6Y60.G4 net (fanout=11) 1.287 pm_fetch_dec_Inst/N87
SLICE_X6Y60.Y Tilo 0.707 pm_fetch_dec_Inst/pc_high<5>
pm_fetch_dec_Inst/I65_mux0000<8>30
SLICE_X6Y60.F4 net (fanout=1) 0.060 pm_fetch_dec_Inst/I65_mux0000<8>30/O
SLICE_X6Y60.CLK Tfck 0.802 pm_fetch_dec_Inst/pc_high<5>
pm_fetch_dec_Inst/I65_mux0000<8>40
pm_fetch_dec_Inst/pc_high_5
------------------------------------------------- ---------------------------
Total 24.914ns (11.875ns logic, 13.039ns route)
(47.7% logic, 52.3% route)
--------------------------------------------------------------------------------
Slack (setup path): -0.962ns (requirement - (data path - clock path skew + uncertainty))
Source: pm_fetch_dec_Inst/push_st (FF)
Destination: pm_fetch_dec_Inst/pc_high_5 (FF)
Requirement: 24.000ns
Data Path Delay: 24.879ns (Levels of Logic = 16)
Clock Path Skew: -0.083ns (0.255 - 0.338)
Source Clock: cp2_BUFGP rising at 0.000ns
Destination Clock: cp2_BUFGP rising at 24.000ns
Clock Uncertainty: 0.000ns
Maximum Data Path: pm_fetch_dec_Inst/push_st to pm_fetch_dec_Inst/pc_high_5
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X8Y36.YQ Tcko 0.676 pm_fetch_dec_Inst/call_st3
pm_fetch_dec_Inst/push_st
SLICE_X9Y35.G3 net (fanout=4) 0.765 pm_fetch_dec_Inst/push_st
SLICE_X9Y35.COUT Topcyg 1.178 pm_fetch_dec_Inst/nop_insert_st_wg_cy<1>
pm_fetch_dec_Inst/nop_insert_st_wg_lut<1>
pm_fetch_dec_Inst/nop_insert_st_wg_cy<1>
SLICE_X9Y36.CIN net (fanout=1) 0.000 pm_fetch_dec_Inst/nop_insert_st_wg_cy<1>
SLICE_X9Y36.COUT Tbyp 0.130 pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>
pm_fetch_dec_Inst/nop_insert_st_wg_cy<2>
pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>
SLICE_X9Y28.G3 net (fanout=13) 1.062 pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>
SLICE_X9Y28.Y Tilo 0.648 pm_fetch_dec_Inst/alu_data_r_in_or0001
pm_fetch_dec_Inst/nop_insert_st_wg_cy<5>1
SLICE_X13Y26.G3 net (fanout=101) 0.773 pm_fetch_dec_Inst/nop_insert_st
SLICE_X13Y26.Y Tilo 0.648 N556
pm_fetch_dec_Inst/reg_rd_adr<3>2
SLICE_X18Y26.G2 net (fanout=3) 0.752 pm_fetch_dec_Inst/reg_rd_adr<3>2
SLICE_X18Y26.Y Tilo 0.707 GPRF_Inst/N188
pm_fetch_dec_Inst/reg_rd_adr<3>47_1
SLICE_X16Y28.G4 net (fanout=14) 0.736 pm_fetch_dec_Inst/reg_rd_adr<3>47
SLICE_X16Y28.Y Tilo 0.707 N603
pm_fetch_dec_Inst/reg_rd_adr<2>62_SW1
SLICE_X17Y28.F1 net (fanout=1) 0.173 N843
SLICE_X17Y28.X Tilo 0.643 GPRF_Inst/N158
GPRF_Inst/sg_tmp_rd_data_31<0>1131
SLICE_X26Y21.F4 net (fanout=7) 1.335 GPRF_Inst/N158
SLICE_X26Y21.X Tilo 0.692 GPRF_Inst/sg_tmp_rd_data_31<2>150
GPRF_Inst/sg_tmp_rd_data_31<2>150
SLICE_X23Y24.F3 net (fanout=1) 0.562 GPRF_Inst/sg_tmp_rd_data_31<2>150
SLICE_X23Y24.X Tilo 0.643 GPRF_Inst/sg_tmp_rd_data_31<2>256
GPRF_Inst/sg_tmp_rd_data_31<2>256
SLICE_X20Y20.G2 net (fanout=2) 0.648 GPRF_Inst/sg_tmp_rd_data_31<2>256
SLICE_X20Y20.Y Tilo 0.707 ALU_Inst/incdec_op_carry<2>
GPRF_Inst/sg_tmp_rd_data_31<2>282_1
SLICE_X19Y31.F3 net (fanout=10) 1.134 GPRF_Inst/sg_tmp_rd_data_31<2>282
SLICE_X19Y31.X Tif5x 0.924 BP_Inst/bit_test_mux_out_7_mux0000184
BP_Inst/bit_test_mux_out_7_mux0000184_G
BP_Inst/bit_test_mux_out_7_mux0000184
SLICE_X6Y44.F2 net (fanout=2) 1.049 BP_Inst/bit_test_mux_out_7_mux0000184
SLICE_X6Y44.X Tilo 0.692 BP_Inst/N01
BP_Inst/bit_test_mux_out_7_mux00001112
SLICE_X4Y57.G4 net (fanout=9) 1.529 BP_Inst/N01
SLICE_X4Y57.Y Tilo 0.707 pm_fetch_dec_Inst/N2
pm_fetch_dec_Inst/brxx_st_and000011
SLICE_X8Y41.F2 net (fanout=13) 1.111 pm_fetch_dec_Inst/cpu_busy_and0000
SLICE_X8Y41.X Tilo 0.692 pm_fetch_dec_Inst/brxx_st
pm_fetch_dec_Inst/I65_mux0000<0>41
SLICE_X6Y60.G4 net (fanout=11) 1.287 pm_fetch_dec_Inst/N87
SLICE_X6Y60.Y Tilo 0.707 pm_fetch_dec_Inst/pc_high<5>
pm_fetch_dec_Inst/I65_mux0000<8>30
SLICE_X6Y60.F4 net (fanout=1) 0.060 pm_fetch_dec_Inst/I65_mux0000<8>30/O
SLICE_X6Y60.CLK Tfck 0.802 pm_fetch_dec_Inst/pc_high<5>
pm_fetch_dec_Inst/I65_mux0000<8>40
pm_fetch_dec_Inst/pc_high_5
------------------------------------------------- ---------------------------
Total 24.879ns (11.903ns logic, 12.976ns route)
(47.8% logic, 52.2% route)
--------------------------------------------------------------------------------
Slack (setup path): -0.894ns (requirement - (data path - clock path skew + uncertainty))
Source: pm_fetch_dec_Inst/nirq_st0 (FF)
Destination: pm_fetch_dec_Inst/pc_high_5 (FF)
Requirement: 24.000ns
Data Path Delay: 24.811ns (Levels of Logic = 16)
Clock Path Skew: -0.083ns (0.588 - 0.671)
Source Clock: cp2_BUFGP rising at 0.000ns
Destination Clock: cp2_BUFGP rising at 24.000ns
Clock Uncertainty: 0.000ns
Maximum Data Path: pm_fetch_dec_Inst/nirq_st0 to pm_fetch_dec_Inst/pc_high_5
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X6Y29.XQ Tcko 0.631 pm_fetch_dec_Inst/nirq_st0
pm_fetch_dec_Inst/nirq_st0
SLICE_X9Y35.F2 net (fanout=6) 0.828 pm_fetch_dec_Inst/nirq_st0
SLICE_X9Y35.COUT Topcyf 1.195 pm_fetch_dec_Inst/nop_insert_st_wg_cy<1>
pm_fetch_dec_Inst/nop_insert_st_wg_lut<0>
pm_fetch_dec_Inst/nop_insert_st_wg_cy<0>
pm_fetch_dec_Inst/nop_insert_st_wg_cy<1>
SLICE_X9Y36.CIN net (fanout=1) 0.000 pm_fetch_dec_Inst/nop_insert_st_wg_cy<1>
SLICE_X9Y36.COUT Tbyp 0.130 pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>
pm_fetch_dec_Inst/nop_insert_st_wg_cy<2>
pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>
SLICE_X9Y28.G3 net (fanout=13) 1.062 pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>
SLICE_X9Y28.Y Tilo 0.648 pm_fetch_dec_Inst/alu_data_r_in_or0001
pm_fetch_dec_Inst/nop_insert_st_wg_cy<5>1
SLICE_X10Y27.F3 net (fanout=101) 0.590 pm_fetch_dec_Inst/nop_insert_st
SLICE_X10Y27.X Tilo 0.692 pm_fetch_dec_Inst/reg_rd_adr<0>23
pm_fetch_dec_Inst/reg_rd_adr<0>23
SLICE_X18Y26.G4 net (fanout=9) 0.788 pm_fetch_dec_Inst/reg_rd_adr<0>23
SLICE_X18Y26.Y Tilo 0.707 GPRF_Inst/N188
pm_fetch_dec_Inst/reg_rd_adr<3>47_1
SLICE_X16Y28.G4 net (fanout=14) 0.736 pm_fetch_dec_Inst/reg_rd_adr<3>47
SLICE_X16Y28.Y Tilo 0.707 N603
pm_fetch_dec_Inst/reg_rd_adr<2>62_SW1
SLICE_X17Y28.F1 net (fanout=1) 0.173 N843
SLICE_X17Y28.X Tilo 0.643 GPRF_Inst/N158
GPRF_Inst/sg_tmp_rd_data_31<0>1131
SLICE_X26Y21.F4 net (fanout=7) 1.335 GPRF_Inst/N158
SLICE_X26Y21.X Tilo 0.692 GPRF_Inst/sg_tmp_rd_data_31<2>150
GPRF_Inst/sg_tmp_rd_data_31<2>150
SLICE_X23Y24.F3 net (fanout=1) 0.562 GPRF_Inst/sg_tmp_rd_data_31<2>150
SLICE_X23Y24.X Tilo 0.643 GPRF_Inst/sg_tmp_rd_data_31<2>256
GPRF_Inst/sg_tmp_rd_data_31<2>256
SLICE_X20Y20.G2 net (fanout=2) 0.648 GPRF_Inst/sg_tmp_rd_data_31<2>256
SLICE_X20Y20.Y Tilo 0.707 ALU_Inst/incdec_op_carry<2>
GPRF_Inst/sg_tmp_rd_data_31<2>282_1
SLICE_X19Y31.F3 net (fanout=10) 1.134 GPRF_Inst/sg_tmp_rd_data_31<2>282
SLICE_X19Y31.X Tif5x 0.924 BP_Inst/bit_test_mux_out_7_mux0000184
BP_Inst/bit_test_mux_out_7_mux0000184_G
BP_Inst/bit_test_mux_out_7_mux0000184
SLICE_X6Y44.F2 net (fanout=2) 1.049 BP_Inst/bit_test_mux_out_7_mux0000184
SLICE_X6Y44.X Tilo 0.692 BP_Inst/N01
BP_Inst/bit_test_mux_out_7_mux00001112
SLICE_X4Y57.G4 net (fanout=9) 1.529 BP_Inst/N01
SLICE_X4Y57.Y Tilo 0.707 pm_fetch_dec_Inst/N2
pm_fetch_dec_Inst/brxx_st_and000011
SLICE_X8Y41.F2 net (fanout=13) 1.111 pm_fetch_dec_Inst/cpu_busy_and0000
SLICE_X8Y41.X Tilo 0.692 pm_fetch_dec_Inst/brxx_st
pm_fetch_dec_Inst/I65_mux0000<0>41
SLICE_X6Y60.G4 net (fanout=11) 1.287 pm_fetch_dec_Inst/N87
SLICE_X6Y60.Y Tilo 0.707 pm_fetch_dec_Inst/pc_high<5>
pm_fetch_dec_Inst/I65_mux0000<8>30
SLICE_X6Y60.F4 net (fanout=1) 0.060 pm_fetch_dec_Inst/I65_mux0000<8>30/O
SLICE_X6Y60.CLK Tfck 0.802 pm_fetch_dec_Inst/pc_high<5>
pm_fetch_dec_Inst/I65_mux0000<8>40
pm_fetch_dec_Inst/pc_high_5
------------------------------------------------- ---------------------------
Total 24.811ns (11.919ns logic, 12.892ns route)
(48.0% logic, 52.0% route)
--------------------------------------------------------------------------------
Hold Paths: TS_cp2 = PERIOD TIMEGRP "cp2" 24 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack (hold path): 0.973ns (requirement - (clock path skew + uncertainty - data path))
Source: pm_fetch_dec_Inst/pc_high_1 (FF)
Destination: pm_fetch_dec_Inst/program_counter_tmp_9 (FF)
Requirement: 0.000ns
Data Path Delay: 1.003ns (Levels of Logic = 0)
Clock Path Skew: 0.030ns (0.281 - 0.251)
Source Clock: cp2_BUFGP rising at 24.000ns
Destination Clock: cp2_BUFGP rising at 24.000ns
Clock Uncertainty: 0.000ns
Minimum Data Path: pm_fetch_dec_Inst/pc_high_1 to pm_fetch_dec_Inst/program_counter_tmp_9
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X7Y59.XQ Tcko 0.473 pm_fetch_dec_Inst/pc_high<1>
pm_fetch_dec_Inst/pc_high_1
SLICE_X4Y61.BX net (fanout=7) 0.392 pm_fetch_dec_Inst/pc_high<1>
SLICE_X4Y61.CLK Tckdi (-Th) -0.138 pm_fetch_dec_Inst/program_counter_tmp<9>
pm_fetch_dec_Inst/program_counter_tmp_9
------------------------------------------------- ---------------------------
Total 1.003ns (0.611ns logic, 0.392ns route)
(60.9% logic, 39.1% route)
--------------------------------------------------------------------------------
Slack (hold path): 1.056ns (requirement - (clock path skew + uncertainty - data path))
Source: pm_fetch_dec_Inst/pc_high_5 (FF)
Destination: pm_fetch_dec_Inst/program_counter_tmp_13 (FF)
Requirement: 0.000ns
Data Path Delay: 1.067ns (Levels of Logic = 0)
Clock Path Skew: 0.011ns (0.065 - 0.054)
Source Clock: cp2_BUFGP rising at 24.000ns
Destination Clock: cp2_BUFGP rising at 24.000ns
Clock Uncertainty: 0.000ns
Minimum Data Path: pm_fetch_dec_Inst/pc_high_5 to pm_fetch_dec_Inst/program_counter_tmp_13
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X6Y60.XQ Tcko 0.505 pm_fetch_dec_Inst/pc_high<5>
pm_fetch_dec_Inst/pc_high_5
SLICE_X6Y63.BX net (fanout=5) 0.424 pm_fetch_dec_Inst/pc_high<5>
SLICE_X6Y63.CLK Tckdi (-Th) -0.138 pm_fetch_dec_Inst/program_counter_tmp<13>
pm_fetch_dec_Inst/program_counter_tmp_13
------------------------------------------------- ---------------------------
Total 1.067ns (0.643ns logic, 0.424ns route)
(60.3% logic, 39.7% route)
--------------------------------------------------------------------------------
Slack (hold path): 1.065ns (requirement - (clock path skew + uncertainty - data path))
Source: pm_fetch_dec_Inst/ramwe_int (FF)
Destination: pm_fetch_dec_Inst/ramwe_int (FF)
Requirement: 0.000ns
Data Path Delay: 1.065ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock: cp2_BUFGP rising at 24.000ns
Destination Clock: cp2_BUFGP rising at 24.000ns
Clock Uncertainty: 0.000ns
Minimum Data Path: pm_fetch_dec_Inst/ramwe_int to pm_fetch_dec_Inst/ramwe_int
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X1Y32.YQ Tcko 0.464 pm_fetch_dec_Inst/ramwe_int
pm_fetch_dec_Inst/ramwe_int
SLICE_X1Y32.BY net (fanout=4) 0.461 pm_fetch_dec_Inst/ramwe_int
SLICE_X1Y32.CLK Tckdi (-Th) -0.140 pm_fetch_dec_Inst/ramwe_int
pm_fetch_dec_Inst/ramwe_int
------------------------------------------------- ---------------------------
Total 1.065ns (0.604ns logic, 0.461ns route)
(56.7% logic, 43.3% route)
--------------------------------------------------------------------------------
Component Switching Limit Checks: TS_cp2 = PERIOD TIMEGRP "cp2" 24 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 20.796ns (period - (min low pulse limit / (low pulse / period)))
Period: 24.000ns
Low pulse: 12.000ns
Low pulse limit: 1.602ns (Trpw)
Physical resource: IORegs_Inst/sreg<2>/SR
Logical resource: IORegs_Inst/sreg_2/SR
Location pin: SLICE_X4Y19.SR
Clock network: ireset_IBUF
--------------------------------------------------------------------------------
Slack: 20.796ns (period - (min high pulse limit / (high pulse / period)))
Period: 24.000ns
High pulse: 12.000ns
High pulse limit: 1.602ns (Trpw)
Physical resource: IORegs_Inst/sreg<2>/SR
Logical resource: IORegs_Inst/sreg_2/SR
Location pin: SLICE_X4Y19.SR
Clock network: ireset_IBUF
--------------------------------------------------------------------------------
Slack: 20.796ns (period - (min low pulse limit / (low pulse / period)))
Period: 24.000ns
Low pulse: 12.000ns
Low pulse limit: 1.602ns (Trpw)
Physical resource: IORegs_Inst/sph<0>/SR
Logical resource: IORegs_Inst/sph_0/SR
Location pin: SLICE_X2Y43.SR
Clock network: ireset_IBUF
--------------------------------------------------------------------------------
1 constraint not met.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Clock to Setup on destination clock cp2
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
cp2 | 24.997| | | |
---------------+---------+---------+---------+---------+
Timing summary:
---------------
Timing errors: 47 Score: 18553 (Setup/Max: 18553, Hold: 0)
Constraints cover 128661977 paths, 0 nets, and 7182 connections
Design statistics:
Minimum period: 24.997ns{1} (Maximum frequency: 40.005MHz)
------------------------------------Footnotes-----------------------------------
1) The minimum period statistic assumes all single cycle delays.
Analysis completed Fri Oct 01 23:50:17 2010
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 145 MB