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[/] [bilinear_demosaic/] [trunk/] [sim/] [rtl_sim/] [work/] [register@delay/] [_primary.vhd] - Rev 2
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library verilog; use verilog.vl_types.all; entity registerDelay is generic( DATA_WIDTH : integer := 8; STAGES : integer := 1 ); port( clk : in vl_logic; rst : in vl_logic; enable : in vl_logic; d : in vl_logic_vector; q : out vl_logic_vector ); end registerDelay;