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##### >>>   UCF File for Xilinx Spartan-3 FPGA Board   <<< #####
### Created by Spartan-3 UCF Generator on 12/28/2005 at 12:26

### Spartan-3 Clock Oscillator:
NET clkin LOC=T9;  # CLK - 50MHz oscillator

### Spartan-3 Pushbutton Switches:
NET pb0 LOC=L14;  # BTN3 (active high)
NET pb1 LOC=L13;  # BTN2 (active high)
NET pb2 LOC=M14;  # BTN1 (active high)
NET pb3 LOC=M13;  # BTN0 (active high)

### Spartan-3 Slide Switches:
NET sw[7] LOC=K13;  # SW7 (active high when up)
NET sw[6] LOC=K14;  # SW6 (active high when up)
NET sw[5] LOC=J13;  # SW5 (active high when up)
NET sw[4] LOC=J14;  # SW4 (active high when up)
NET sw[3] LOC=H13;  # SW3 (active high when up)
NET sw[2] LOC=H14;  # SW2 (active high when up)
NET sw[1] LOC=G12;  # SW1 (active high when up)
NET sw[0] LOC=F12;  # SW0 (active high when up)



### Spartan-3 Discrete LEDs:
NET led[7] LOC=P11;  # LD7 (active high)
NET led[6] LOC=P12;  # LD6 (active high)
NET led[5] LOC=N12;  # LD5 (active high)
NET led[4] LOC=P13;  # LD4 (active high)
NET led[3] LOC=N14;  # LD3 (active high)
NET led[2] LOC=L12;  # LD2 (active high)
NET led[1] LOC=P14;  # LD1 (active high)
NET led[0] LOC=K12;  # LD0 (active high)


### Spartan-3 7-Segment LED:   digit enables:
NET digsel[3] LOC=E13;  # left digit (active low)
NET digsel[2] LOC=F14;  # middle left digit (active low)
NET digsel[1] LOC=G14;  # middle right digit (active low)
NET digsel[0] LOC=D14;  # right digit (active low)

### Spartan-3 7-Segment LED:   segment enables:
NET display[0] LOC=E14;  # LED display segment a (active low)
NET display[1] LOC=G13;  # LED display segment b (active low)
NET display[2] LOC=N15;  # LED display segment c (active low)
NET display[3] LOC=P15;  # LED display segment d (active low)
NET display[4] LOC=R16;  # LED display segment e (active low)
NET display[5] LOC=F13;  # LED display segment f (active low)
NET display[6] LOC=N16;  # LED display segment g (active low)
NET dp LOC=P16;  # LED display decimal point (active low)




CONFIG PROHIBIT=T13;
CONFIG PROHIBIT=R13;


CONFIG PROHIBIT=N10;
CONFIG PROHIBIT=T14;


CONFIG PROHIBIT=M16;
CONFIG PROHIBIT=M15;


CONFIG PROHIBIT=R12;
CONFIG PROHIBIT=T12;
CONFIG PROHIBIT=R11;
CONFIG PROHIBIT=R9;
CONFIG PROHIBIT=T10;


### Spartan-3 SRAM:Enables for IC10:
NET xmce LOC=P7;  # CE1 - chip enable (active low)
NET xmub LOC=T4;  # UB1 - upper byte enable (active low)
NET xmlb LOC=P6;  # LB1 - lower byte enable (active low)


CONFIG PROHIBIT=N5;
CONFIG PROHIBIT=R4;
CONFIG PROHIBIT=P5;

### Spartan-3 SRAM:Enables for both IC10 and IC11:
NET xmsend LOC=K4;  # OE - output enable (active low)
NET xmwrite LOC=G3;  # WE - write enable (active low)

### Spartan-3 SRAM:Address for both IC10 and IC11:
NET xmaddress[17] LOC=L3;  # A17
NET xmaddress[16] LOC=K5;  # A16
NET xmaddress[15] LOC=K3;  # A15
NET xmaddress[14] LOC=J3;  # A14
NET xmaddress[13] LOC=J4;  # A13
NET xmaddress[12] LOC=H4;  # A12
NET xmaddress[11] LOC=H3;  # A11
NET xmaddress[10] LOC=G5;  # A10
NET xmaddress[9] LOC=E4;  # A9
NET xmaddress[8] LOC=E3;  # A8
NET xmaddress[7] LOC=F4;  # A7
NET xmaddress[6] LOC=F3;  # A6
NET xmaddress[5] LOC=G4;  # A5
NET xmaddress[4] LOC=L4;  # A4
NET xmaddress[3] LOC=M3;  # A3
NET xmaddress[2] LOC=M4;  # A2
NET xmaddress[1] LOC=N3;  # A1
NET xmaddress[0] LOC=L5;  # A0

### Spartan-3 SRAM:Data for IC10:
NET xmdata[15] LOC=R1;  # D15
NET xmdata[14] LOC=P1;  # D14
NET xmdata[13] LOC=L2;  # D13
NET xmdata[12] LOC=J2;  # D12
NET xmdata[11] LOC=H1;  # D11
NET xmdata[10] LOC=F2;  # D10
NET xmdata[9] LOC=P8;  # D9
NET xmdata[8] LOC=D3;  # D8
NET xmdata[7] LOC=B1;  # D7
NET xmdata[6] LOC=C1;  # D6
NET xmdata[5] LOC=C2;  # D5
NET xmdata[4] LOC=R5;  # D4
NET xmdata[3] LOC=T5;  # D3
NET xmdata[2] LOC=R6;  # D2
NET xmdata[1] LOC=T8;  # D1
NET xmdata[0] LOC=N7;  # D0


CONFIG PROHIBIT=N1;
CONFIG PROHIBIT=M1;
CONFIG PROHIBIT=K2;
CONFIG PROHIBIT=C3;
CONFIG PROHIBIT=F5;
CONFIG PROHIBIT=G1;
CONFIG PROHIBIT=E2;
CONFIG PROHIBIT=D2;
CONFIG PROHIBIT=D1;
CONFIG PROHIBIT=E1;
CONFIG PROHIBIT=G2;
CONFIG PROHIBIT=J1;
CONFIG PROHIBIT=K1;
CONFIG PROHIBIT=M2;
CONFIG PROHIBIT=N2;
CONFIG PROHIBIT=P2;