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$date
    Fri Dec  9 00:05:57 2005
$end
$version
    GPLCVER_2.11a of 07/05/05
$end
$timescale
    1 ns
$end
$scope module t_alu $end
$scope module U0 $end
$var wire       1 !    a2 $end
$var wire       1 #    aand $end
$var wire       1 %    abar $end
$var wire       1 '    aor $end
$var wire       1 )    asum $end
$var wire       1 +    axor $end
$var reg      16 -    dout [15:0] $end
$var wire       1 /    overflow $end
$var wire      16 1    y [15:0] $end
$var wire      16 3    z [15:0] $end
$upscope $end
$upscope $end
$scope module t_control $end
$scope module U0 $end
$var wire       1 5    aluov $end
$var wire       1 7    clk $end
$var reg       3 9    counter [2:0] $end
$var wire       8 ;    cp [8:1] $end
$var wire       1 =    cycle $end
$var wire       1 ?    deposit $end
$var wire       1 A    estate $end
$var wire       1 C    exam $end
$var wire       1 E    extdeposit $end
$var wire       1 G    extexam $end
$var wire       1 I    extstart $end
$var wire       1 K    extstop $end
$var wire       1 M    ihlt $end
$var wire       1 O    pende $end
$var wire       1 Q    pstop $end
$var wire       1 S    start $end
$var wire       1 U    statee $end
$var wire       1 W    stop $end
$var wire       1 Y    xdep $end
$var wire       1 [    xexam $end
$var wire       1 ]    xrun $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
x!
x#
x%
x'
x)
x+
bz -
x/
bx 1
bx 3
05
07
b0 9
b0 ;
0=
x?
0A
xC
0E
0G
0I
0K
0M
0O
0Q
xS
0U
xW
0Y
0[
0]
$end
#1
b10101010 3
b1010101 1
#2
0/
b11111111 -
0?
0C
0W
0S
1)
17
#3
bz -
0)
#4
b11111111 -
1'
07
#5
bz -
0'
#6
b0 -
1#
17
#7
bz -
0#
#8
b1111111101010101 -
1%
07
#9
bz -
0%
#10
b101010100 -
1S
1!
17
1I
#11
bz -
0!
#12
b111111111000000 3
07
#13
b1000000000010101 -
1/
1)
#14
1]
bz -
0S
b111 9
0/
0)
17
#15