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[/] [blue/] [trunk/] [blue8/] [dla.cdc] - Rev 7

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#ChipScope Core Inserter Project File Version 3.0
#Mon Oct 09 17:44:37 CDT 2006
Project.device.designInputFile=C\:\\blue8\\topbox_cs.ngc
Project.device.designOutputFile=C\:\\blue8\\topbox_cs.ngc
Project.device.deviceFamily=6
Project.device.enableRPMs=true
Project.device.outputDirectory=C\:\\blue8\\_ngo
Project.device.useSRL16=true
Project.filter.dimension=2
Project.filter<0>=*run*
Project.filter<1>=
Project.icon.boundaryScanChain=0
Project.icon.disableBUFGInsertion=false
Project.icon.enableExtTriggerIn=false
Project.icon.enableExtTriggerOut=false
Project.icon.triggerInPinName=
Project.icon.triggerOutPinName=
Project.unit.dimension=1
Project.unit<0>.clockChannel=clk
Project.unit<0>.clockEdge=Rising
Project.unit<0>.dataChannel<0>=CPU/pc/areg/regvalue<0>
Project.unit<0>.dataChannel<10>=CPU/pc/areg/regvalue<10>
Project.unit<0>.dataChannel<11>=CPU/pc/areg/regvalue<11>
Project.unit<0>.dataChannel<12>=CPU/acc/regvalue<0>
Project.unit<0>.dataChannel<13>=CPU/acc/regvalue<1>
Project.unit<0>.dataChannel<14>=CPU/acc/regvalue<2>
Project.unit<0>.dataChannel<15>=CPU/acc/regvalue<3>
Project.unit<0>.dataChannel<16>=CPU/acc/regvalue<4>
Project.unit<0>.dataChannel<17>=CPU/acc/regvalue<5>
Project.unit<0>.dataChannel<18>=CPU/acc/regvalue<6>
Project.unit<0>.dataChannel<19>=CPU/acc/regvalue<7>
Project.unit<0>.dataChannel<1>=CPU/pc/areg/regvalue<1>
Project.unit<0>.dataChannel<20>=CPU/acc/regvalue<8>
Project.unit<0>.dataChannel<21>=CPU/acc/regvalue<9>
Project.unit<0>.dataChannel<22>=CPU/acc/regvalue<10>
Project.unit<0>.dataChannel<23>=CPU/acc/regvalue<11>
Project.unit<0>.dataChannel<24>=CPU/acc/regvalue<12>
Project.unit<0>.dataChannel<25>=CPU/acc/regvalue<13>
Project.unit<0>.dataChannel<26>=CPU/acc/regvalue<14>
Project.unit<0>.dataChannel<27>=CPU/acc/regvalue<15>
Project.unit<0>.dataChannel<28>=CPU/IR/regvalue<0>
Project.unit<0>.dataChannel<29>=CPU/IR/regvalue<1>
Project.unit<0>.dataChannel<2>=CPU/pc/areg/regvalue<2>
Project.unit<0>.dataChannel<30>=CPU/IR/regvalue<2>
Project.unit<0>.dataChannel<31>=CPU/IR/regvalue<3>
Project.unit<0>.dataChannel<32>=CPU/IR/regvalue<4>
Project.unit<0>.dataChannel<33>=CPU/IR/regvalue<5>
Project.unit<0>.dataChannel<34>=CPU/IR/regvalue<6>
Project.unit<0>.dataChannel<35>=CPU/IR/regvalue<7>
Project.unit<0>.dataChannel<36>=CPU/IR/regvalue<8>
Project.unit<0>.dataChannel<37>=CPU/IR/regvalue<9>
Project.unit<0>.dataChannel<38>=CPU/IR/regvalue<10>
Project.unit<0>.dataChannel<39>=CPU/IR/regvalue<11>
Project.unit<0>.dataChannel<3>=CPU/pc/areg/regvalue<3>
Project.unit<0>.dataChannel<40>=CPU/IR/regvalue<12>
Project.unit<0>.dataChannel<41>=CPU/IR/regvalue<13>
Project.unit<0>.dataChannel<42>=CPU/IR/regvalue<14>
Project.unit<0>.dataChannel<43>=CPU/IR/regvalue<15>
Project.unit<0>.dataChannel<4>=CPU/pc/areg/regvalue<4>
Project.unit<0>.dataChannel<5>=CPU/pc/areg/regvalue<5>
Project.unit<0>.dataChannel<6>=CPU/pc/areg/regvalue<6>
Project.unit<0>.dataChannel<7>=CPU/pc/areg/regvalue<7>
Project.unit<0>.dataChannel<8>=CPU/pc/areg/regvalue<8>
Project.unit<0>.dataChannel<9>=CPU/pc/areg/regvalue<9>
Project.unit<0>.dataDepth=512
Project.unit<0>.dataEqualsTrigger=false
Project.unit<0>.dataPortWidth=44
Project.unit<0>.enableGaps=false
Project.unit<0>.enableStorageQualification=true
Project.unit<0>.enableTimestamps=false
Project.unit<0>.timestampDepth=0
Project.unit<0>.timestampWidth=0
Project.unit<0>.triggerChannel<0><0>=CPU/pc/areg/regvalue<0>
Project.unit<0>.triggerChannel<0><10>=CPU/pc/areg/regvalue<10>
Project.unit<0>.triggerChannel<0><11>=CPU/pc/areg/regvalue<11>
Project.unit<0>.triggerChannel<0><1>=CPU/pc/areg/regvalue<1>
Project.unit<0>.triggerChannel<0><2>=CPU/pc/areg/regvalue<2>
Project.unit<0>.triggerChannel<0><3>=CPU/pc/areg/regvalue<3>
Project.unit<0>.triggerChannel<0><4>=CPU/pc/areg/regvalue<4>
Project.unit<0>.triggerChannel<0><5>=CPU/pc/areg/regvalue<5>
Project.unit<0>.triggerChannel<0><6>=CPU/pc/areg/regvalue<6>
Project.unit<0>.triggerChannel<0><7>=CPU/pc/areg/regvalue<7>
Project.unit<0>.triggerChannel<0><8>=CPU/pc/areg/regvalue<8>
Project.unit<0>.triggerChannel<0><9>=CPU/pc/areg/regvalue<9>
Project.unit<0>.triggerChannel<1><0>=CPU/ctl/sim/RUN/q
Project.unit<0>.triggerConditionCountWidth=0
Project.unit<0>.triggerMatchCount<0>=1
Project.unit<0>.triggerMatchCount<1>=1
Project.unit<0>.triggerMatchCountWidth<0><0>=0
Project.unit<0>.triggerMatchCountWidth<1><0>=0
Project.unit<0>.triggerMatchType<0><0>=0
Project.unit<0>.triggerMatchType<1><0>=0
Project.unit<0>.triggerPortCount=2
Project.unit<0>.triggerPortIsData<0>=true
Project.unit<0>.triggerPortIsData<1>=true
Project.unit<0>.triggerPortWidth<0>=12
Project.unit<0>.triggerPortWidth<1>=1
Project.unit<0>.triggerSequencerLevels=16
Project.unit<0>.triggerSequencerType=1
Project.unit<0>.type=ilapro

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