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version 3
c:\blue71\uart.v
uart
VERILOG
VERILOG
tbuart.xwv
Clocked
-
-
10000000000
ns
GSR:true
PRLD:false
40000000
CLOCK_LIST_BEGIN
clk
20000000
20000000
2000000
2000000
40000000
RISING
CLOCK_LIST_END
SIGNAL_LIST_BEGIN
data_ready
clk
din
clk
dout
clk
framing_error
clk
rdn
clk
rst
clk
rxd
clk
sdo
clk
tbre
clk
tsre
clk
wrn
clk
SIGNAL_LIST_END
SIGNALS_NOT_ON_DISPLAY
data_ready_DIFF
dout_DIFF
framing_error_DIFF
sdo_DIFF
tbre_DIFF
tsre_DIFF
SIGNALS_NOT_ON_DISPLAY_END
MARKER_LIST_BEGIN
MARKER_LIST_END
MEASURE_LIST_BEGIN
MEASURE_LIST_END
SIGNAL_ORDER_BEGIN
clk
rdn
rst
rxd
wrn
din
data_ready
framing_error
sdo
tbre
tsre
dout
SIGNAL_ORDER_END
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