Subversion Repositories bu_pacman

Release 10.1 par K.31 (nt)
Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.

ECE-PHO115-15::  Sun Nov 23 21:13:11 2008

par -w -intstyle ise -ol std -t 1 Display_Controller_map.ncd
Display_Controller.ncd Display_Controller.pcf 


Constraints file: Display_Controller.pcf.
Loading device for application Rf_Device from file '3s1000.nph' in environment C:\Xilinx\10.1\ISE.
   "Display_Controller" is an NCD, version 3.2, device xc3s1000, package ft256, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)

INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
   -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
   internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For
   the fastest runtime, set the effort level to "std".  For best performance, set the effort level to "high". For a
   balance between the fastest runtime and best performance, set the effort level to "med".

Device speed data version:  "PRODUCTION 1.39 2008-01-09".


Device Utilization Summary:

   Number of BUFGMUXs                        3 out of 8      37%
   Number of External IOBs                  44 out of 173    25%
      Number of LOCed IOBs                  44 out of 44    100%

   Number of RAMB16s                        15 out of 24     62%
   Number of Slices                        235 out of 7680    3%
      Number of SLICEMs                      0 out of 3840    0%



Overall effort level (-ol):   Standard 
Placer effort level (-pl):    High 
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard 


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:98a01b) REAL time: 1 secs 

Phase 2.7
Phase 2.7 (Checksum:1312cfe) REAL time: 1 secs 

Phase 3.31
Phase 3.31 (Checksum:1c9c37d) REAL time: 1 secs 

Phase 4.2

.
Phase 4.2 (Checksum:26259fc) REAL time: 1 secs 

Phase 5.8
........................................
.....................
....
.
Phase 5.8 (Checksum:a0c827) REAL time: 6 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 6 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 7 secs 

Phase 8.5
Phase 8.5 (Checksum:4c4b3f8) REAL time: 7 secs 

REAL time consumed by placer: 7 secs 
CPU  time consumed by placer: 6 secs 
Writing design to file Display_Controller.ncd


Total REAL time to Placer completion: 7 secs 
Total CPU time to Placer completion: 6 secs 

Starting Router

Phase 1: 2040 unrouted;       REAL time: 10 secs 

Phase 2: 1783 unrouted;       REAL time: 10 secs 

Phase 3: 350 unrouted;       REAL time: 11 secs 

Phase 4: 350 unrouted; (545263)      REAL time: 11 secs 

Phase 5: 343 unrouted; (0)      REAL time: 15 secs 

Phase 6: 0 unrouted; (0)      REAL time: 15 secs 

Phase 7: 0 unrouted; (0)      REAL time: 15 secs 

Phase 8: 0 unrouted; (0)      REAL time: 15 secs 

WARNING:Route:455 - CLK Net:clk3/div_clk may have excessive skew because 
      0 CLK pins and 1 NON_CLK pins failed to route using a CLK template.

Total REAL time to Router completion: 15 secs 
Total CPU time to Router completion: 12 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|        clk2/div_clk |      BUFGMUX6| No   |   70 |  0.343     |  1.046      |
+---------------------+--------------+------+------+------------+-------------+
|        clk1/div_clk |      BUFGMUX5| No   |  103 |  0.334     |  1.072      |
+---------------------+--------------+------+------+------------+-------------+
|           clk_BUFGP |      BUFGMUX0| No   |    2 |  0.191     |  0.994      |
+---------------------+--------------+------+------+------------+-------------+
|        clk3/div_clk |         Local|      |    9 |  0.026     |  2.639      |
+---------------------+--------------+------+------+------------+-------------+
|  vga2/count_and0000 |         Local|      |    1 |  0.000     |  0.827      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.

Timing Score: 0

INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no
   requested value.
Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

------------------------------------------------------------------------------------------------------
  Constraint                                |  Check  | Worst Case |  Best Case | Timing |   Timing   
                                            |         |    Slack   | Achievable | Errors |    Score   
------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net clk | SETUP   |         N/A|     9.013ns|     N/A|           0
  2/div_clk                                 | HOLD    |     0.806ns|            |       0|           0
------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net clk | SETUP   |         N/A|     9.708ns|     N/A|           0
  1/div_clk                                 | HOLD    |     0.806ns|            |       0|           0
------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net clk | SETUP   |         N/A|     5.416ns|     N/A|           0
  3/div_clk                                 | HOLD    |     1.154ns|            |       0|           0
------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net vga | SETUP   |         N/A|     2.040ns|     N/A|           0
  2/count_and0000                           | HOLD    |     1.150ns|            |       0|           0
------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net clk | SETUP   |         N/A|     4.229ns|     N/A|           0
  _BUFGP                                    | HOLD    |     0.825ns|            |       0|           0
------------------------------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the 
   constraint does not cover any paths or that it has no requested value.


Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 28 secs 
Total CPU time to PAR completion: 14 secs 

Peak Memory Usage:  137 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 1
Number of info messages: 2

Writing design to file Display_Controller.ncd



PAR done!