URL
https://opencores.org/ocsvn/bu_pacman/bu_pacman/trunk
Subversion Repositories bu_pacman
[/] [bu_pacman/] [tags/] [arelease/] [Display_Controller.syr] - Rev 6
Compare with Previous | Blame | View Log
Release 10.1 - xst K.31 (nt)Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.--> Parameter TMPDIR set to X:/Display_Controller/xst/projnav.tmpTotal REAL time to Xst completion: 0.00 secsTotal CPU time to Xst completion: 0.20 secs--> Parameter xsthdpdir set to X:/Display_Controller/xstTotal REAL time to Xst completion: 0.00 secsTotal CPU time to Xst completion: 0.20 secs--> Reading design: Display_Controller.prjTABLE OF CONTENTS1) Synthesis Options Summary2) HDL Compilation3) Design Hierarchy Analysis4) HDL Analysis5) HDL Synthesis5.1) HDL Synthesis Report6) Advanced HDL Synthesis6.1) Advanced HDL Synthesis Report7) Low Level Synthesis8) Partition Report9) Final Report9.1) Device utilization summary9.2) Partition Resource Summary9.3) TIMING REPORT=========================================================================* Synthesis Options Summary *=========================================================================---- Source ParametersInput File Name : "Display_Controller.prj"Input Format : mixedIgnore Synthesis Constraint File : NO---- Target ParametersOutput File Name : "Display_Controller"Output Format : NGCTarget Device : xc3s1000-4-ft256---- Source OptionsTop Module Name : Display_ControllerAutomatic FSM Extraction : YESFSM Encoding Algorithm : AutoSafe Implementation : NoFSM Style : lutRAM Extraction : YesRAM Style : AutoROM Extraction : YesMux Style : AutoDecoder Extraction : YESPriority Encoder Extraction : YESShift Register Extraction : YESLogical Shifter Extraction : YESXOR Collapsing : YESROM Style : AutoMux Extraction : YESResource Sharing : YESAsynchronous To Synchronous : NOMultiplier Style : autoAutomatic Register Balancing : No---- Target OptionsAdd IO Buffers : YESGlobal Maximum Fanout : 500Add Generic Clock Buffer(BUFG) : 8Register Duplication : YESSlice Packing : YESOptimize Instantiated Primitives : NOUse Clock Enable : YesUse Synchronous Set : YesUse Synchronous Reset : YesPack IO Registers into IOBs : autoEquivalent register Removal : YES---- General OptionsOptimization Goal : SpeedOptimization Effort : 1Library Search Order : Display_Controller.lsoKeep Hierarchy : NONetlist Hierarchy : as_optimizedRTL Output : YesGlobal Optimization : AllClockNetsRead Cores : YESWrite Timing Constraints : NOCross Clock Analysis : NOHierarchy Separator : /Bus Delimiter : <>Case Specifier : maintainSlice Utilization Ratio : 100BRAM Utilization Ratio : 100Verilog 2001 : YESAuto BRAM Packing : NOSlice Utilization Ratio Delta : 5==================================================================================================================================================* HDL Compilation *=========================================================================Compiling verilog file "vga_display.v" in library workCompiling verilog file "vga_controller.v" in library workModule <vga_display> compiledCompiling verilog file "generate_add.v" in library workModule <vga_controller> compiledCompiling verilog file "./fifo_generator_v4_3.v" in library workModule <generate_add> compiledCompiling verilog file "color_fsm.v" in library workModule <fifo_generator_v4_3> compiledCompiling verilog file "clock_divider.v" in library workModule <color_fsm> compiledCompiling verilog file "Display_Controller.v" in library workModule <clk_divider> compiledModule <Display_Controller> compiledNo errors in compilationAnalysis of file <"Display_Controller.prj"> succeeded.=========================================================================* Design Hierarchy Analysis *=========================================================================Analyzing hierarchy for module <Display_Controller> in library <work>.Analyzing hierarchy for module <clk_divider> in library <work> with parameters.NBIT = "00000000000000000000000000000010"NDIV = "00000000000000000000000000000010"Analyzing hierarchy for module <clk_divider> in library <work> with parameters.NBIT = "00000000000000000000000000000100"NDIV = "00000000000000000000000000001010"Analyzing hierarchy for module <clk_divider> in library <work> with parameters.NBIT = "00000000000000000000000000000101"NDIV = "00000000000000000000000000010100"Analyzing hierarchy for module <vga_controller> in library <work> with parameters.HFP = "00000000000000000000001010001000"HLINES = "00000000000000000000001010000000"HMAX = "00000000000000000000001100100000"HSP = "00000000000000000000001011101000"SPP = "00000000000000000000000000000000"VFP = "00000000000000000000000111100010"VLINES = "00000000000000000000000111100000"VMAX = "00000000000000000000001000001101"VSP = "00000000000000000000000111100100"Analyzing hierarchy for module <color_fsm> in library <work> with parameters.pixel_1 = "000"pixel_2 = "001"pixel_3 = "010"pixel_4 = "011"pixel_5 = "100"xpos_end = "111000000"xpos_start = "011000000"ypos_end = "110110000"ypos_start = "000110000"Analyzing hierarchy for module <vga_display> in library <work> with parameters.score_pos = "111000010"xpos_end = "111000000"xpos_start = "011000000"ypos_end = "110110000"ypos_start = "000110000"Analyzing hierarchy for module <generate_add> in library <work>.=========================================================================* HDL Analysis *=========================================================================Analyzing top module <Display_Controller>.WARNING:Xst:2211 - "./fifo_generator_v4_3.v" line 48: Instantiating black box module <fifo_generator_v4_3>.Module <Display_Controller> is correct for synthesis.Analyzing module <clk_divider.1> in library <work>.NBIT = 32'sb00000000000000000000000000000010NDIV = 32'sb00000000000000000000000000000010Module <clk_divider.1> is correct for synthesis.Analyzing module <clk_divider.2> in library <work>.NBIT = 32'sb00000000000000000000000000000100NDIV = 32'sb00000000000000000000000000001010Module <clk_divider.2> is correct for synthesis.Analyzing module <clk_divider.3> in library <work>.NBIT = 32'sb00000000000000000000000000000101NDIV = 32'sb00000000000000000000000000010100Module <clk_divider.3> is correct for synthesis.Analyzing module <vga_controller> in library <work>.HFP = 32'sb00000000000000000000001010001000HLINES = 32'sb00000000000000000000001010000000HMAX = 32'sb00000000000000000000001100100000HSP = 32'sb00000000000000000000001011101000SPP = 32'sb00000000000000000000000000000000VFP = 32'sb00000000000000000000000111100010VLINES = 32'sb00000000000000000000000111100000VMAX = 32'sb00000000000000000000001000001101VSP = 32'sb00000000000000000000000111100100Module <vga_controller> is correct for synthesis.Analyzing module <color_fsm> in library <work>.pixel_1 = 3'b000pixel_2 = 3'b001pixel_3 = 3'b010pixel_4 = 3'b011pixel_5 = 3'b100xpos_end = 9'b111000000xpos_start = 9'b011000000ypos_end = 9'b110110000ypos_start = 9'b000110000WARNING:Xst:905 - "color_fsm.v" line 52: One or more signals are missing in the sensitivity list of always block. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:<count>, <hcount>, <vcount>Module <color_fsm> is correct for synthesis.Analyzing module <vga_display> in library <work>.score_pos = 9'b111000010xpos_end = 9'b111000000xpos_start = 9'b011000000ypos_end = 9'b110110000ypos_start = 9'b000110000Module <vga_display> is correct for synthesis.Analyzing module <generate_add> in library <work>.Module <generate_add> is correct for synthesis.=========================================================================* HDL Synthesis *=========================================================================Performing bidirectional port resolution...Synthesizing Unit <clk_divider_1>.Related source file is "clock_divider.v".Found 1-bit register for signal <div_clk>.Found 2-bit up counter for signal <count>.Found 2-bit comparator greatequal for signal <count$cmp_ge0000> created at line 38.Found 2-bit comparator greater for signal <div_clk$cmp_gt0000> created at line 40.Summary:inferred 1 Counter(s).inferred 1 D-type flip-flop(s).inferred 2 Comparator(s).Unit <clk_divider_1> synthesized.Synthesizing Unit <clk_divider_2>.Related source file is "clock_divider.v".Found 1-bit register for signal <div_clk>.Found 4-bit up counter for signal <count>.Found 4-bit comparator greatequal for signal <count$cmp_ge0000> created at line 38.Found 4-bit comparator greater for signal <div_clk$cmp_gt0000> created at line 40.Summary:inferred 1 Counter(s).inferred 1 D-type flip-flop(s).inferred 2 Comparator(s).Unit <clk_divider_2> synthesized.Synthesizing Unit <clk_divider_3>.Related source file is "clock_divider.v".Found 1-bit register for signal <div_clk>.Found 5-bit up counter for signal <count>.Found 5-bit comparator greatequal for signal <count$cmp_ge0000> created at line 38.Found 5-bit comparator greater for signal <div_clk$cmp_gt0000> created at line 40.Summary:inferred 1 Counter(s).inferred 1 D-type flip-flop(s).inferred 2 Comparator(s).Unit <clk_divider_3> synthesized.Synthesizing Unit <vga_controller>.Related source file is "vga_controller.v".Found 1-bit register for signal <HS>.Found 11-bit up counter for signal <hcounter>.Found 11-bit up counter for signal <vcounter>.Found 1-bit register for signal <VS>.Found 1-bit register for signal <blank>.Found 11-bit comparator greatequal for signal <HS$cmp_ge0000> created at line 60.Found 11-bit comparator less for signal <HS$cmp_lt0000> created at line 60.Found 11-bit comparator less for signal <video_enable$cmp_lt0000> created at line 67.Found 11-bit comparator less for signal <video_enable$cmp_lt0001> created at line 67.Found 11-bit comparator greatequal for signal <VS$cmp_ge0000> created at line 64.Found 11-bit comparator less for signal <VS$cmp_lt0000> created at line 64.Summary:inferred 2 Counter(s).inferred 3 D-type flip-flop(s).inferred 6 Comparator(s).Unit <vga_controller> synthesized.Synthesizing Unit <color_fsm>.Related source file is "color_fsm.v".WARNING:Xst:647 - Input <pixel_set_rgb<15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <clk_2MHz> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.Found finite state machine <FSM_0> for signal <pixel_state>.-----------------------------------------------------------------------| States | 5 || Transitions | 9 || Inputs | 1 || Outputs | 5 || Clock | clk_20MHz (rising_edge) || Clock enable | pixel_state$not0000 (positive) || Power Up State | 000 || Encoding | automatic || Implementation | LUT |-----------------------------------------------------------------------WARNING:Xst:737 - Found 1-bit latch for signal <count>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.Found 1-bit register for signal <blue_in>.Found 1-bit register for signal <write_fifo>.Found 1-bit register for signal <green_in>.Found 1-bit register for signal <read_fifo>.Found 1-bit register for signal <red_in>.Found 11-bit comparator greatequal for signal <pixel_state$cmp_ge0000> created at line 74.Found 11-bit comparator greatequal for signal <pixel_state$cmp_ge0001> created at line 73.Found 11-bit comparator less for signal <pixel_state$cmp_lt0000> created at line 74.Found 11-bit comparator less for signal <pixel_state$cmp_lt0001> created at line 73.Summary:inferred 1 Finite State Machine(s).inferred 5 D-type flip-flop(s).inferred 4 Comparator(s).Unit <color_fsm> synthesized.Synthesizing Unit <vga_display>.Related source file is "vga_display.v".Found 1-bit register for signal <blue_out>.Found 1-bit register for signal <red_out>.Found 1-bit register for signal <green_out>.Found 11-bit comparator greatequal for signal <red_out$cmp_ge0000> created at line 52.Found 11-bit comparator greatequal for signal <red_out$cmp_ge0001> created at line 53.Found 11-bit comparator less for signal <red_out$cmp_lt0000> created at line 52.Found 11-bit comparator less for signal <red_out$cmp_lt0001> created at line 53.Summary:inferred 3 D-type flip-flop(s).inferred 4 Comparator(s).Unit <vga_display> synthesized.Synthesizing Unit <generate_add>.Related source file is "generate_add.v".Found 16-bit up counter for signal <addr>.Summary:inferred 1 Counter(s).Unit <generate_add> synthesized.Synthesizing Unit <Display_Controller>.Related source file is "Display_Controller.v".Unit <Display_Controller> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# Counters : 611-bit up counter : 216-bit up counter : 12-bit up counter : 14-bit up counter : 15-bit up counter : 1# Registers : 141-bit register : 14# Latches : 11-bit latch : 1# Comparators : 2011-bit comparator greatequal : 611-bit comparator less : 82-bit comparator greatequal : 12-bit comparator greater : 14-bit comparator greatequal : 14-bit comparator greater : 15-bit comparator greatequal : 15-bit comparator greater : 1==================================================================================================================================================* Advanced HDL Synthesis *=========================================================================Analyzing FSM <FSM_0> for best encoding.Optimizing FSM <vga2/pixel_state> on signal <pixel_state[1:3]> with gray encoding.-------------------State | Encoding-------------------000 | 000001 | 001010 | 011011 | 010100 | 110-------------------Loading device for application Rf_Device from file '3s1000.nph' in environment C:\Xilinx\10.1\ISE.Reading core <fifo_generator_v4_3.ngc>.Loading core <fifo_generator_v4_3> for timing and area information for instance <fifo1>.WARNING:Xst:1426 - The value init of the FF/Latch 0 hinder the constant cleaning in the block count.You should achieve better results by setting this init to 1.=========================================================================Advanced HDL Synthesis ReportMacro Statistics# Counters : 611-bit up counter : 216-bit up counter : 12-bit up counter : 14-bit up counter : 15-bit up counter : 1# Registers : 17Flip-Flops : 17# Latches : 11-bit latch : 1# Comparators : 2011-bit comparator greatequal : 611-bit comparator less : 82-bit comparator greatequal : 12-bit comparator greater : 14-bit comparator greatequal : 14-bit comparator greater : 15-bit comparator greatequal : 15-bit comparator greater : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================WARNING:Xst:1426 - The value init of the FF/Latch count hinder the constant cleaning in the block color_fsm.You should achieve better results by setting this init to 1.Optimizing unit <Display_Controller> ...Optimizing unit <color_fsm> ...Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block Display_Controller, actual ratio is 2.INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/wr_rst_reg_1> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/wr_rst_reg_0>INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/rd_rst_reg_2> in Unit <BU2> is equivalent to the following 2 FFs/Latches : <U0/grf.rf/rstblk/rd_rst_reg_1> <U0/grf.rf/rstblk/rd_rst_reg_0>INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i>INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i>INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/wr_rst_reg_1> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/wr_rst_reg_0>INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/rd_rst_reg_2> in Unit <BU2> is equivalent to the following 2 FFs/Latches : <U0/grf.rf/rstblk/rd_rst_reg_1> <U0/grf.rf/rstblk/rd_rst_reg_0>INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i>INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i>Final Macro Processing ...=========================================================================Final Register ReportMacro Statistics# Registers : 66Flip-Flops : 66==================================================================================================================================================* Partition Report *=========================================================================Partition Implementation Status-------------------------------No Partitions were found in this design.-------------------------------=========================================================================* Final Report *=========================================================================Final ResultsRTL Top Level Output File Name : Display_Controller.ngrTop Level Output File Name : Display_ControllerOutput Format : NGCOptimization Goal : SpeedKeep Hierarchy : NODesign Statistics# IOs : 44Cell Usage :# BELS : 510# GND : 2# INV : 9# LUT1 : 63# LUT2 : 52# LUT2_L : 8# LUT3 : 60# LUT3_D : 2# LUT3_L : 3# LUT4 : 108# LUT4_D : 5# LUT4_L : 11# MUXCY : 95# MUXF5 : 18# MUXF6 : 9# VCC : 2# XORCY : 63# FlipFlops/Latches : 267# FD : 4# FDC : 112# FDCE : 67# FDE : 14# FDP : 9# FDPE : 5# FDR : 44# FDRE : 11# LDE : 1# RAMS : 15# RAMB16_S1_S1 : 7# RAMB16_S9_S9 : 8# Clock Buffers : 3# BUFG : 2# BUFGP : 1# IO Buffers : 43# IBUF : 1# OBUF : 42=========================================================================Device utilization summary:---------------------------Selected Device : 3s1000ft256-4Number of Slices: 221 out of 7680 2%Number of Slice Flip Flops: 267 out of 15360 1%Number of 4 input LUTs: 321 out of 15360 2%Number of IOs: 44Number of bonded IOBs: 44 out of 173 25%Number of BRAMs: 15 out of 24 62%Number of GCLKs: 3 out of 8 37%---------------------------Partition Resource Summary:---------------------------No Partitions were found in this design.---------------------------=========================================================================TIMING REPORTNOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORTGENERATED AFTER PLACE-and-ROUTE.Clock Information:-------------------------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-------------------------------------------------+------------------------+-------+clk2/div_clk1 | BUFG | 103 |clk1/div_clk1 | BUFG | 160 |clk | BUFGP | 3 |clk3/div_clk | NONE(add1/addr_0) | 16 |vga2/count_and0000(vga2/count_and0000_wg_cy<5>:O)| NONE(*)(vga2/count) | 1 |-------------------------------------------------+------------------------+-------+(*) This 1 clock signal(s) are generated by combinatorial logic,and XST is not able to identify which are the primary clock signals.Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.Asynchronous Control Signals Information:---------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------+-------+Control Signal | Buffer(FF name) | Load |-----------------------------------------------------------------------------------+------------------------------------------------------+-------+fifo1/BU2/U0/grf.rf/rstblk/rd_rst_reg<1>(fifo1/BU2/U0/grf.rf/rstblk/rd_rst_reg_1:Q)| NONE(fifo1/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_9)| 56 |fifo1/BU2/U0/grf.rf/rstblk/wr_rst_reg<0>(fifo1/BU2/U0/grf.rf/rstblk/wr_rst_reg_0:Q)| NONE(fifo1/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_4)| 56 |fifo1/BU2/U0/grf.rf/rstblk/wr_rst_reg<1>(fifo1/BU2/U0/grf.rf/rstblk/wr_rst_reg_1:Q)| NONE(fifo1/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i)| 44 |fifo1/BU2/U0/grf.rf/rstblk/rd_rst_reg<2>(fifo1/BU2/U0/grf.rf/rstblk/rd_rst_reg_2:Q)| NONE(fifo1/BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_0) | 30 |fifo1/BU2/U0/grf.rf/rstblk/rd_rst_comb(fifo1/BU2/U0/grf.rf/rstblk/rd_rst_comb1:O) | NONE(fifo1/BU2/U0/grf.rf/rstblk/rd_rst_reg_2) | 3 |fifo1/BU2/U0/grf.rf/rstblk/wr_rst_comb(fifo1/BU2/U0/grf.rf/rstblk/wr_rst_comb1:O) | NONE(fifo1/BU2/U0/grf.rf/rstblk/wr_rst_reg_1) | 2 |reset | IBUF | 2 |-----------------------------------------------------------------------------------+------------------------------------------------------+-------+Timing Summary:---------------Speed Grade: -4Minimum period: 7.055ns (Maximum Frequency: 141.743MHz)Minimum input arrival time before clock: 5.937nsMaximum output required time after clock: 8.839nsMaximum combinational path delay: No path foundTiming Detail:--------------All values displayed in nanoseconds (ns)=========================================================================Timing constraint: Default period analysis for Clock 'clk2/div_clk1'Clock period: 5.855ns (frequency: 170.794MHz)Total number of paths / destination ports: 555 / 213-------------------------------------------------------------------------Delay: 5.855ns (Levels of Logic = 2)Source: fifo1/BU2/U0/grf.rf/rstblk/rd_rst_reg_0 (FF)Destination: fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[14].ram.r/v2_noinit.ram/dp9x9.ram (RAM)Source Clock: clk2/div_clk1 risingDestination Clock: clk2/div_clk1 risingData Path: fifo1/BU2/U0/grf.rf/rstblk/rd_rst_reg_0 to fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[14].ram.r/v2_noinit.ram/dp9x9.ramGate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------FDP:C->Q 16 0.720 1.305 U0/grf.rf/rstblk/rd_rst_reg_0 (U0/grf.rf/rstblk/rd_rst_reg<0>)LUT3:I2->O 18 0.551 1.443 U0/grf.rf/mem/tmp_ram_rd_en1 (U0/grf.rf/mem/tmp_ram_rd_en)LUT4:I3->O 1 0.551 0.801 U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/bindec_b.bindec_inst_b/enout_7_mux00001 (U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/enb_array<7>)RAMB16_S9_S9:ENB 0.484 U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[14].ram.r/v2_noinit.ram/dp9x9.ram----------------------------------------Total 5.855ns (2.306ns logic, 3.549ns route)(39.4% logic, 60.6% route)=========================================================================Timing constraint: Default period analysis for Clock 'clk1/div_clk1'Clock period: 7.055ns (frequency: 141.743MHz)Total number of paths / destination ports: 1524 / 329-------------------------------------------------------------------------Delay: 7.055ns (Levels of Logic = 3)Source: vga1/vcounter_0 (FF)Destination: vga1/vcounter_0 (FF)Source Clock: clk1/div_clk1 risingDestination Clock: clk1/div_clk1 risingData Path: vga1/vcounter_0 to vga1/vcounter_0Gate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------FDRE:C->Q 3 0.720 1.246 vga1/vcounter_0 (vga1/vcounter_0)LUT4:I0->O 1 0.551 1.140 vga1/vcounter_or000010 (vga1/vcounter_or000010)LUT4_L:I0->LO 1 0.551 0.126 vga1/vcounter_or000075_SW0 (N27)LUT4:I3->O 11 0.551 1.144 vga1/vcounter_or000075 (vga1/vcounter_or0000)FDRE:R 1.026 vga1/vcounter_0----------------------------------------Total 7.055ns (3.399ns logic, 3.656ns route)(48.2% logic, 51.8% route)=========================================================================Timing constraint: Default period analysis for Clock 'clk'Clock period: 4.430ns (frequency: 225.734MHz)Total number of paths / destination ports: 9 / 5-------------------------------------------------------------------------Delay: 4.430ns (Levels of Logic = 1)Source: clk1/count_0 (FF)Destination: clk1/count_0 (FF)Source Clock: clk risingDestination Clock: clk risingData Path: clk1/count_0 to clk1/count_0Gate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------FDR:C->Q 4 0.720 1.256 clk1/count_0 (clk1/count_0)LUT2:I0->O 2 0.551 0.877 clk1/count_cmp_ge00001 (clk1/count_cmp_ge0000)FDR:R 1.026 clk1/count_0----------------------------------------Total 4.430ns (2.297ns logic, 2.133ns route)(51.9% logic, 48.1% route)=========================================================================Timing constraint: Default period analysis for Clock 'clk3/div_clk'Clock period: 6.327ns (frequency: 158.053MHz)Total number of paths / destination ports: 392 / 32-------------------------------------------------------------------------Delay: 6.327ns (Levels of Logic = 2)Source: add1/addr_6 (FF)Destination: add1/addr_0 (FF)Source Clock: clk3/div_clk risingDestination Clock: clk3/div_clk risingData Path: add1/addr_6 to add1/addr_0Gate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------FDR:C->Q 3 0.720 1.246 add1/addr_6 (add1/addr_6)LUT4:I0->O 1 0.551 0.996 add1/addr_and000016 (add1/addr_and000016)LUT4:I1->O 16 0.551 1.237 add1/addr_and000059 (add1/addr_and0000)FDR:R 1.026 add1/addr_0----------------------------------------Total 6.327ns (2.848ns logic, 3.479ns route)(45.0% logic, 55.0% route)=========================================================================Timing constraint: Default period analysis for Clock 'vga2/count_and0000'Clock period: 3.797ns (frequency: 263.366MHz)Total number of paths / destination ports: 1 / 1-------------------------------------------------------------------------Delay: 3.797ns (Levels of Logic = 1)Source: vga2/count (LATCH)Destination: vga2/count (LATCH)Source Clock: vga2/count_and0000 fallingDestination Clock: vga2/count_and0000 fallingData Path: vga2/count to vga2/countGate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------LDE:G->Q 10 0.633 1.134 vga2/count (vga2/count)INV:I->O 2 0.551 0.877 vga2/read_memory1_INV_0 (read_memory_OBUF)LDE:GE 0.602 vga2/count----------------------------------------Total 3.797ns (1.786ns logic, 2.011ns route)(47.0% logic, 53.0% route)=========================================================================Timing constraint: Default OFFSET IN BEFORE for Clock 'clk1/div_clk1'Total number of paths / destination ports: 37 / 34-------------------------------------------------------------------------Offset: 5.937ns (Levels of Logic = 3)Source: reset (PAD)Destination: vga2/pixel_state_FFd3 (FF)Destination Clock: clk1/div_clk1 risingData Path: reset to vga2/pixel_state_FFd3Gate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------IBUF:I->O 13 0.821 1.365 reset_IBUF (reset_IBUF)LUT2:I1->O 1 0.551 1.140 vga2/red_in_not0001296_SW1 (N24)LUT4:I0->O 3 0.551 0.907 vga2/pixel_state_not00011 (vga2/pixel_state_not0001)FDE:CE 0.602 vga2/pixel_state_FFd3----------------------------------------Total 5.937ns (2.525ns logic, 3.412ns route)(42.5% logic, 57.5% route)=========================================================================Timing constraint: Default OFFSET OUT AFTER for Clock 'vga2/count_and0000'Total number of paths / destination ports: 2 / 2-------------------------------------------------------------------------Offset: 8.839ns (Levels of Logic = 2)Source: vga2/count (LATCH)Destination: read_memory (PAD)Source Clock: vga2/count_and0000 fallingData Path: vga2/count to read_memoryGate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------LDE:G->Q 10 0.633 1.134 vga2/count (vga2/count)INV:I->O 2 0.551 0.877 vga2/read_memory1_INV_0 (read_memory_OBUF)OBUF:I->O 5.644 read_memory_OBUF (read_memory)----------------------------------------Total 8.839ns (6.828ns logic, 2.011ns route)(77.2% logic, 22.8% route)=========================================================================Timing constraint: Default OFFSET OUT AFTER for Clock 'clk1/div_clk1'Total number of paths / destination ports: 6 / 6-------------------------------------------------------------------------Offset: 7.241ns (Levels of Logic = 2)Source: fifo1/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i (FF)Destination: fifo_full (PAD)Source Clock: clk1/div_clk1 risingData Path: fifo1/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i to fifo_fullGate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------FDP:C->Q 2 0.720 0.877 U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i (full)end scope: 'BU2'end scope: 'fifo1'OBUF:I->O 5.644 fifo_full_OBUF (fifo_full)----------------------------------------Total 7.241ns (6.364ns logic, 0.877ns route)(87.9% logic, 12.1% route)=========================================================================Timing constraint: Default OFFSET OUT AFTER for Clock 'clk2/div_clk1'Total number of paths / destination ports: 1 / 1-------------------------------------------------------------------------Offset: 7.241ns (Levels of Logic = 2)Source: fifo1/BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i (FF)Destination: fifo_empty (PAD)Source Clock: clk2/div_clk1 risingData Path: fifo1/BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i to fifo_emptyGate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------FDP:C->Q 2 0.720 0.877 U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i (empty)end scope: 'BU2'end scope: 'fifo1'OBUF:I->O 5.644 fifo_empty_OBUF (fifo_empty)----------------------------------------Total 7.241ns (6.364ns logic, 0.877ns route)(87.9% logic, 12.1% route)=========================================================================Timing constraint: Default OFFSET OUT AFTER for Clock 'clk3/div_clk'Total number of paths / destination ports: 16 / 16-------------------------------------------------------------------------Offset: 7.271ns (Levels of Logic = 1)Source: add1/addr_15 (FF)Destination: addr<15> (PAD)Source Clock: clk3/div_clk risingData Path: add1/addr_15 to addr<15>Gate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------FDR:C->Q 3 0.720 0.907 add1/addr_15 (add1/addr_15)OBUF:I->O 5.644 addr_15_OBUF (addr<15>)----------------------------------------Total 7.271ns (6.364ns logic, 0.907ns route)(87.5% logic, 12.5% route)=========================================================================Total REAL time to Xst completion: 16.00 secsTotal CPU time to Xst completion: 15.63 secs-->Total memory usage is 159604 kilobytesNumber of errors : 0 ( 0 filtered)Number of warnings : 8 ( 0 filtered)Number of infos : 9 ( 0 filtered)