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[/] [bu_pacman/] [tags/] [arelease/] [Display_Controller.twr] - Rev 7
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Release 10.1 Trace (nt)
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
C:\Xilinx\10.1\ISE\bin\nt\unwrapped\trce.exe -ise
X:/Display_Controller/Display_Controller.ise -intstyle ise -e 3 -s 4 -xml
Display_Controller Display_Controller.ncd -o Display_Controller.twr
Display_Controller.pcf -ucf vga_pins.ucf
Design file: Display_Controller.ncd
Physical constraint file: Display_Controller.pcf
Device,package,speed: xc3s1000,ft256,-4 (PRODUCTION 1.39 2008-01-09)
Report level: error report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk | 4.229| | | |
---------------+---------+---------+---------+---------+
Analysis completed Sun Nov 23 21:13:53 2008
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Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 91 MB
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