URL
https://opencores.org/ocsvn/bu_pacman/bu_pacman/trunk
Subversion Repositories bu_pacman
[/] [bu_pacman/] [tags/] [arelease/] [Display_Controller_map.mrp] - Rev 6
Compare with Previous | Blame | View Log
Release 10.1 Map K.31 (nt)Xilinx Mapping Report File for Design 'Display_Controller'Design Information------------------Command Line : map -ise X:/Display_Controller/Display_Controller.ise -intstyleise -p xc3s1000-ft256-4 -cm area -pr off -k 4 -c 100 -oDisplay_Controller_map.ncd Display_Controller.ngd Display_Controller.pcfTarget Device : xc3s1000Target Package : ft256Target Speed : -4Mapper Version : spartan3 -- $Revision: 1.1.1.1 $Mapped Date : Sun Nov 23 21:12:37 2008Design Summary--------------Number of errors: 0Number of warnings: 1Logic Utilization:Total Number Slice Registers: 267 out of 15,360 1%Number used as Flip Flops: 266Number used as Latches: 1Number of 4 input LUTs: 248 out of 15,360 1%Logic Distribution:Number of occupied Slices: 235 out of 7,680 3%Number of Slices containing only related logic: 235 out of 235 100%Number of Slices containing unrelated logic: 0 out of 235 0%*See NOTES below for an explanation of the effects of unrelated logic.Total Number of 4 input LUTs: 311 out of 15,360 2%Number used as logic: 248Number used as a route-thru: 63Number of bonded IOBs: 44 out of 173 25%Number of RAMB16s: 15 out of 24 62%Number of BUFGMUXs: 3 out of 8 37%Peak Memory Usage: 139 MBTotal REAL time to MAP completion: 13 secsTotal CPU time to MAP completion: 2 secsNOTES:Related logic is defined as being logic that shares connectivity - e.g. twoLUTs are "related" if they share common inputs. When assembling slices,Map gives priority to combine logic that is related. Doing so results inthe best timing performance.Unrelated logic shares no connectivity. Map will only begin packingunrelated logic into a slice once 99% of the slices are occupied throughrelated logic packing.Note that once logic distribution reaches the 99% level through relatedlogic packing, this does not mean the device is completely utilized.Unrelated logic packing will then begin, continuing until all usable LUTsand FFs are occupied. Depending on your timing budget, increased levels ofunrelated logic packing may adversely affect the overall timing performanceof your design.Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group and Partition SummarySection 10 - Modular Design SummarySection 11 - Timing ReportSection 12 - Configuration String InformationSection 13 - Control Set InformationSection 14 - Utilization by HierarchySection 1 - Errors------------------Section 2 - Warnings--------------------WARNING:LIT:243 - Logical network fifo1/dout<15> has no load.Section 3 - Informational-------------------------INFO:MapLib:562 - No environment variables are currently set.INFO:MapLib:986 - The SAVE constraint for nets has been made more strictstarting in 10.1, such that the net driver and load blocks will be preservedas well. To revert to the original behavior please set XIL_MAP_OLD_SAVE.INFO:MapLib:984 - SAVE has been detected on the following signal(s):reset,clk.INFO:LIT:244 - All of the single ended outputs in this design are using slewrate limited output drivers. The delay on speed critical single ended outputscan be dramatically reduced by designating them as fast outputs.Section 4 - Removed Logic Summary---------------------------------9 block(s) removed4 block(s) optimized away15 signal(s) removedSection 5 - Removed Logic-------------------------The trimmed logic report below shows the logic removed from your design due tosourceless or loadless signals, and VCC or ground connections. If the removalof a signal or symbol results in the subsequent removal of an additional signalor symbol, the message explaining that second removal will be indented. Thisindentation will be repeated as a chain of related logic is removed.To quickly locate the original cause for the removal of a chain of logic, lookabove the place where that logic is listed in the trimming report, then locatethe lines that are least indented (begin at the leftmost edge).The signal "fifo1/dout<15>" is sourceless and has been removed.The signal"fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ram_doutb12<8>" is sourceless and has been removed.Sourceless block"fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/has_mux_b.B/Mmux_dout_mux_45" (ROM) removed.The signal"fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/has_mux_b.B/Mmux_dout_mux_45" is sourceless and has been removed.Sourceless block"fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f5_4" (MUX) removed.The signal"fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f55" is sourceless and has been removed.Sourceless block"fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f6_4" (MUX) removed.The signal"fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ram_doutb13<8>" is sourceless and has been removed.The signal"fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ram_doutb10<8>" is sourceless and has been removed.Sourceless block"fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/has_mux_b.B/Mmux_dout_mux_510" (ROM) removed.The signal"fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/has_mux_b.B/Mmux_dout_mux_510" is sourceless and has been removed.The signal"fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ram_doutb11<8>" is sourceless and has been removed.The signal"fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ram_doutb8<8>" is sourceless and has been removed.Sourceless block"fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/has_mux_b.B/Mmux_dout_mux_511" (ROM) removed.The signal"fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/has_mux_b.B/Mmux_dout_mux_511" is sourceless and has been removed.Sourceless block"fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f5_4" (MUX) removed.The signal"fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f55" is sourceless and has been removed.The signal"fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ram_doutb9<8>" is sourceless and has been removed.The signal"fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ram_doutb6<8>" is sourceless and has been removed.Sourceless block"fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/has_mux_b.B/Mmux_dout_mux_65" (ROM) removed.The signal"fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/has_mux_b.B/Mmux_dout_mux_65" is sourceless and has been removed.The signal"fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ram_doutb7<8>" is sourceless and has been removed.Unused block "fifo1/GND" (ZERO) removed.Unused block "fifo1/VCC" (ONE) removed.Optimized Block(s):TYPE BLOCKGND XST_GNDVCC XST_VCCGND fifo1/BU2/XST_GNDVCC fifo1/BU2/XST_VCCTo enable printing of redundant blocks removed and signals merged, set thedetailed map report option and rerun map.Section 6 - IOB Properties--------------------------+----------------------------------------------------------------------------------------------------------------------------------------+| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB || | | | | Strength | Rate | | | Delay |+----------------------------------------------------------------------------------------------------------------------------------------+| addr<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || addr<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || addr<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || addr<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || addr<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || addr<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || addr<6> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || addr<7> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || addr<8> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || addr<9> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || addr<10> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || addr<11> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || addr<12> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || addr<13> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || addr<14> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || addr<15> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || blue_out | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || chip_enable | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || clk | IOB | INPUT | LVCMOS25 | | | | | || fifo_empty | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || fifo_full | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || green_out | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || h_sync | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || pixel_color<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || pixel_color<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || pixel_color<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || pixel_color<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || pixel_color<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || pixel_color<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || pixel_color<6> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || pixel_color<7> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || pixel_color<8> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || pixel_color<9> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || pixel_color<10> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || pixel_color<11> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || pixel_color<12> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || pixel_color<13> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || pixel_color<14> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || pixel_color<15> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || read_memory | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || red_out | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || reset | IOB | INPUT | LVCMOS25 | | | | | || v_sync | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || write_memory | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |+----------------------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group and Partition Summary--------------------------------------------Partition Implementation Status-------------------------------No Partitions were found in this design.-------------------------------Area Group Information----------------------No area groups were found in this design.----------------------Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------This design was not run using timing mode.Section 12 - Configuration String Details-----------------------------------------Use the "-detail" map option to print out Configuration StringsSection 13 - Control Set Information------------------------------------No control set information for this architecture.Section 14 - Utilization by Hierarchy-------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+| Module | Partition | Slices | Slice Reg | LUTs | LUTRAM | BRAM | MULT18X18 | BUFG | DCM | Full Hierarchical Name |+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+| Display_Controller/ | | 55/301 | 0/267 | 66/311 | 0/0 | 0/15 | 0/0 | 1/3 | 0/0 | Display_Controller || +add1 | | 12/12 | 16/16 | 6/6 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | Display_Controller/add1 || +clk1 | | 3/3 | 3/3 | 3/3 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | Display_Controller/clk1 || +clk2 | | 4/4 | 5/5 | 5/5 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | Display_Controller/clk2 || +clk3 | | 5/5 | 6/6 | 5/5 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | Display_Controller/clk3 || +fifo1 | | 0/164 | 0/200 | 0/157 | 0/0 | 0/15 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1 || ++BU2 | | 0/164 | 0/200 | 0/157 | 0/0 | 0/15 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2 || +++U0 | | 0/164 | 0/200 | 0/157 | 0/0 | 0/15 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0 || ++++grf.rf | | 0/164 | 0/200 | 0/157 | 0/0 | 0/15 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf || +++++gcx.clkx | | 68/68 | 112/112 | 74/74 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/gcx.clkx || +++++gl0.rd | | 1/25 | 0/30 | 1/16 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/gl0.rd || ++++++gras.rsts | | 2/10 | 2/2 | 1/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/gl0.rd/gras.rsts || +++++++c0 | | 4/4 | 0/0 | 7/7 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/gl0.rd/gras.rsts/c0 || +++++++c1 | | 4/4 | 0/0 | 7/7 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/gl0.rd/gras.rsts/c1 || ++++++rpntr | | 14/14 | 28/28 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/gl0.rd/rpntr || +++++gl0.wr | | 1/32 | 0/44 | 1/16 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/gl0.wr || ++++++gwas.wsts | | 2/10 | 2/2 | 1/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/gl0.wr/gwas.wsts || +++++++c1 | | 4/4 | 0/0 | 7/7 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1 || +++++++c2 | | 4/4 | 0/0 | 7/7 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2 || ++++++wpntr | | 21/21 | 42/42 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/gl0.wr/wpntr || +++++mem | | 1/30 | 0/3 | 1/49 | 0/0 | 0/15 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/mem || ++++++gbm.gbmg.gbmga.ngecc.bmg | | 0/29 | 0/3 | 0/48 | 0/0 | 0/15 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg || +++++++blk_mem_generator | | 0/29 | 0/3 | 0/48 | 0/0 | 0/15 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator || ++++++++valid.cstr | | 0/29 | 0/3 | 0/48 | 0/0 | 0/15 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr || +++++++++bindec_a.bindec_inst_ | | 5/5 | 0/0 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/bindec_a.bindec_inst_a || +++++++++bindec_b.bindec_inst_ | | 6/6 | 0/0 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/bindec_b.bindec_inst_b || +++++++++has_mux_b.B | | 18/18 | 3/3 | 32/32 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/has_mux_b.B || +++++++++ramloop[0].ram.r | | 0/0 | 0/0 | 0/0 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r || ++++++++++v2_noinit.ram | | 0/0 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram || +++++++++ramloop[10].ram.r | | 0/0 | 0/0 | 0/0 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[10].ram.r || ++++++++++v2_noinit.ram | | 0/0 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[10].ram.r/v2_noinit.ram || +++++++++ramloop[11].ram.r | | 0/0 | 0/0 | 0/0 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[11].ram.r || ++++++++++v2_noinit.ram | | 0/0 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[11].ram.r/v2_noinit.ram || +++++++++ramloop[12].ram.r | | 0/0 | 0/0 | 0/0 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[12].ram.r || ++++++++++v2_noinit.ram | | 0/0 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[12].ram.r/v2_noinit.ram || +++++++++ramloop[13].ram.r | | 0/0 | 0/0 | 0/0 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[13].ram.r || ++++++++++v2_noinit.ram | | 0/0 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[13].ram.r/v2_noinit.ram || +++++++++ramloop[14].ram.r | | 0/0 | 0/0 | 0/0 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[14].ram.r || ++++++++++v2_noinit.ram | | 0/0 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[14].ram.r/v2_noinit.ram || +++++++++ramloop[1].ram.r | | 0/0 | 0/0 | 0/0 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r || ++++++++++v2_noinit.ram | | 0/0 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/v2_noinit.ram || +++++++++ramloop[2].ram.r | | 0/0 | 0/0 | 0/0 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[2].ram.r || ++++++++++v2_noinit.ram | | 0/0 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[2].ram.r/v2_noinit.ram || +++++++++ramloop[3].ram.r | | 0/0 | 0/0 | 0/0 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[3].ram.r || ++++++++++v2_noinit.ram | | 0/0 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[3].ram.r/v2_noinit.ram || +++++++++ramloop[4].ram.r | | 0/0 | 0/0 | 0/0 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[4].ram.r || ++++++++++v2_noinit.ram | | 0/0 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[4].ram.r/v2_noinit.ram || +++++++++ramloop[5].ram.r | | 0/0 | 0/0 | 0/0 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[5].ram.r || ++++++++++v2_noinit.ram | | 0/0 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[5].ram.r/v2_noinit.ram || +++++++++ramloop[6].ram.r | | 0/0 | 0/0 | 0/0 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[6].ram.r || ++++++++++v2_noinit.ram | | 0/0 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[6].ram.r/v2_noinit.ram || +++++++++ramloop[7].ram.r | | 0/0 | 0/0 | 0/0 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[7].ram.r || ++++++++++v2_noinit.ram | | 0/0 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[7].ram.r/v2_noinit.ram || +++++++++ramloop[8].ram.r | | 0/0 | 0/0 | 0/0 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[8].ram.r || ++++++++++v2_noinit.ram | | 0/0 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[8].ram.r/v2_noinit.ram || +++++++++ramloop[9].ram.r | | 0/0 | 0/0 | 0/0 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[9].ram.r || ++++++++++v2_noinit.ram | | 0/0 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[9].ram.r/v2_noinit.ram || +++++rstblk | | 9/9 | 11/11 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | Display_Controller/fifo1/BU2/U0/grf.rf/rstblk || +vga1 | | 27/27 | 25/25 | 22/22 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | Display_Controller/vga1 || +vga2 | | 21/21 | 9/9 | 31/31 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | Display_Controller/vga2 || +vga3 | | 10/10 | 3/3 | 16/16 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | Display_Controller/vga3 |+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+* Slices can be packed with basic elements from multiple hierarchies.Therefore, a slice will be counted in every hierarchical modulethat each of its packed basic elements belong to.** For each column, there are two numbers reported <A>/<B>.<A> is the number of elements that belong to that specific hierarchical module.<B> is the total number of elements from that hierarchical module and any lower levelhierarchical modules below.*** The LUTRAM column counts all LUTs used as memory including RAM, ROM, and shift registers.