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o <?xml version = '1.0' encoding = 'UTF-8'?> <report-views version="1.5" > <header> <DateModified>2008-11-20T19:48:22</DateModified> <ModuleName>test_memory</ModuleName> <SummaryTimeStamp>Unknown</SummaryTimeStamp> <DateInitialized>2008-11-20T19:48:22</DateInitialized> </header> <body> <viewgroup label="Design Overview" > <view program="implementation" ShowPartitionData="true" type="FPGASummary" inputState="Unknown" file="test_memory_summary.html" label="Summary" > <toc-item title="Design Overview" target="Design Overview" /> <toc-item title="Design Utilization Summary" target="Design Utilization Summary" /> <toc-item title="Performance Summary" target="Performance Summary" /> <toc-item title="Failing Constraints" target="Failing Constraints" /> <toc-item title="Detailed Reports" target="Detailed Reports" /> </view> <view hidden="true" program="implementation" type="HTML" inputState="Unknown" file="test_memory_partitions.html" label="Partition Report" > <view program="map" type="IOBProperties" inputState="Translated" file="test_memory_map.mrp" label="IOB Properties" /> <view program="map" type="Module_Utilization" inputState="Translated" file="test_memory_map.mrp" label="Module Level Utilization" /> <view program="par" type="ConstraintsData" inputState="Mapped" file="test_memory.par" label="Timing Constraints" /> <view program="par" type="PinoutData" inputState="Mapped" file="test_memory.pad" label="Pinout Report" /> <view program="par" type="ClocksData" inputState="Mapped" file="test_memory.par" label="Clock Report" /> </viewgroup> <viewgroup label="Errors and Warnings" > <view program="xst" type="MessageList" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" hideColumns="Filtered" /> <view program="ngdbuild" type="MessageList" inputState="Synthesized" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" hideColumns="Filtered" /> <view program="map" type="MessageList" inputState="Translated" file="_xmsgs/map.xmsgs" label="MapMessages" hideColumns="Filtered" /> <view program="par" type="MessageList" inputState="Mapped" file="_xmsgs/par.xmsgs" label="Place and Route Messages" hideColumns="Filtered" /> <view program="trce" type="MessageList" inputState="Routed" file="_xmsgs/trce.xmsgs" label="Timing Messages" hideColumns="Filtered" /> <view hidden="true" program="xpwr" type="MessageList" inputState="Routed" file="_xmsgs/xpwr.xmsgs" label="Power Messages" hideColumns="Filtered" /> <view program="bitgen" type="MessageList" inputState="Routed" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" hideColumns="Filtered" /> <view fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" program="implementation" type="MessageList" inputState="Current" file="_xmsgs/*.xmsgs" label="All Current Messages" hideColumns="Filtered" /> <viewgroup label="Detailed Reports" > <view program="xst" type="Report" file="test_memory.syr" label="Synthesis Report " > <toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " /> <toc-item title="HDL Compilation" target=" HDL Compilation " /> <toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " /> <toc-item title="HDL Analysis" target=" HDL Analysis " /> <toc-item title="HDL Synthesis" target=" HDL Synthesis " /> <toc-item title="Advanced HDL Synthesis" target=" Advanced HDL Synthesis " /> <toc-item title="Low Level Synthesis" target=" Low Level Synthesis " /> <toc-item title="Partition Report" target=" Partition Report " /> <toc-item title="Final Report" target=" Final Report " /> <view program="ngdbuild" type="Report" inputState="Synthesized" file="test_memory.bld" label="Translation Report" > <toc-item title="Top of Report" target="Release" /> <toc-item title="Command Line" target="Command Line:" /> <toc-item title="Partition Status" target="Partition Implementation Status"/> <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" /> <view program="map" type="Report" inputState="Translated" file="test_memory_map.mrp" label="Map Report" > <toc-item title="Section 1: Errors" target="Section 1 - " /> <toc-item title="Section 2: Warnings" target="Section 2 - " /> <toc-item title="Section 3: Infos" target="Section 3 - " /> <toc-item title="Section 4: Removed Logic Summary" target="Section 4 - " /> <toc-item title="Section 5: Removed Logic" target="Section 5 - " /> <toc-item title="Section 6: IOB Properties" target="Section 6 - " /> <toc-item title="Section 7: RPMs" target="Section 7 - " /> <toc-item title="Section 8: Guide Report" target="Section 8 - " /> <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 - " /> <toc-item title="Section 10: Modular Design Summary" target="Section 10 - " /> <toc-item title="Section 11: Timing Report" target="Section 11 - " /> <toc-item title="Section 12: Configuration String Details" target="Section 12 - " /> <toc-item title="Section 13: Control Set Information" target="Section 13 - " /> <toc-item title="Section 14: Utilization by Hierarchy" target="Section 14 - " /> <view program="par" type="Report" inputState="Mapped" file="test_memory.par" label="Place and Route Report" > <toc-item title="Device Utilization" target="Device Utilization Summary:" /> <toc-item title="Placer Information" target="Starting Placer" /> <toc-item title="Router Information" target="Starting Router" /> <toc-item title="Clock Report" target="Generating Clock Report" /> <toc-item title="Timing Results" target="Timing Score:" /> <toc-item title="Final Summary" target="Peak Memory Usage:" /> <view program="trce" type="Report" inputState="Routed" file="test_memory.twr" label="Static Timing Report" > <toc-item title="Data Sheet Report" target="Data Sheet" /> <toc-item title="Timing Summary" target="Timing summary:" /> <view hidden="true" program="xpwr" type="Report" inputState="Routed" file="test_memory.pwr" label="Power Report" > <toc-item title="Power summary" target="Power summary" /> <toc-item title="Thermal summary" target="Thermal summary" /> <view program="bitgen" type="Report" inputState="Routed" file="test_memory.bgn" label="Bitgen Report" > <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" /> <toc-item title="Final Summary" target="DRC detected" /> <viewgroup label="Secondary Reports" > <view hidden="true" program="isim" type="Secondary_Report" inputState="PreSynthesized" file="isim.log" label="ISIM Simulator Log" /> <view hidden="true" program="netgen" type="Secondary_Report" inputState="Synthesized" file="netgen/synthesis/test_memory_synthesis.nlf" label="Post-Synthesis Simulation Model Report" /> <view hidden="true" program="map" type="Secondary_Report" inputState="Translated" file="test_memory_map.map" label="Map Log File" > <toc-item title="Design Information" target="Design Information" /> <toc-item title="Design Summary" target="Design Summary" /> <view hidden="true" program="xplorer" type="Secondary_Report" inputState="Routed" file="test_memory_xplorer.rpt" label="Xplorer Report" /> <view hidden="true" program="netgen" type="Secondary_Report" inputState="Translated" file="netgen/translate/test_memory_translate.nlf" label="Post-Translate Simulation Model Report" /> <view hidden="true" program="netgen" type="Secondary_Report" inputState="Translated" file="test_memory_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" /> <view hidden="true" program="trce" type="Secondary_Report" inputState="Mapped" file="test_memory_preroute.twr" label="Post-Map Static Timing Report" /> <view hidden="true" program="netgen" type="Secondary_Report" inputState="Mapped" file="netgen/map/test_memory_map.nlf" label="Post-Map Simulation Model Report" /> <view hidden="true" program="map" type="Secondary_Report" inputState="Mapped" file="test_memory_map.psr" label="Physical Synthesis Report" /> <view hidden="true" program="par" type="Pad_Report" inputState="Mapped" file="test_memory_pad.txt" label="Pad Report" /> <view hidden="true" program="par" type="Secondary_Report" inputState="Mapped" file="test_memory.unroutes" label="Unroutes Report" /> <view hidden="true" program="par" type="Secondary_Report" inputState="Mapped" file="test_memory.grf" label="Guide Results Report" /> <view hidden="true" program="par" type="Secondary_Report" inputState="Routed" file="test_memory.dly" label="Asynchronous Delay Report" /> <view hidden="true" program="par" type="Secondary_Report" inputState="Routed" file="test_memory.clk_rgn" label="Clock Region Report" /> <view hidden="true" program="netgen" type="Secondary_Report" inputState="Routed" file="test_memory_par_fecn.nlf" label="Post-Place and Route Formality Netlist" /> <view hidden="true" program="netgen" type="Secondary_Report" inputState="Routed" file="netgen/par/test_memory_timesim.nlf" label="Post-Place and Route Simulation Model Report" /> <view hidden="true" program="netgen" type="Secondary_Report" inputState="Routed" file="test_memory_sta.nlf" label="Primetime Netlist Report" /> <view hidden="true" program="ibiswriter" type="Secondary_Report" inputState="Routed" file="test_memory.ibs" label="IBIS Model" > <toc-item title="Top of Report" target="Xilinx Virtex IBIS File" /> <toc-item title="Component" target="Component " /> <view hidden="true" program="pin2ucf" type="Secondary_Report" inputState="Routed" file="test_memory.lck" label="Back-annotate Pin Report" > <toc-item title="Top of Report" target="pin2ucf Report File" /> <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" /> <view hidden="true" program="pin2ucf" type="Secondary_Report" inputState="Routed" file="test_memory.lpc" label="Locked Pin Constraints" > <toc-item title="Newly Added Constraints" target="The following constraints were newly added" /> </body> </report-views>