Subversion Repositories bu_pacman

<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
     by the Xilinx ISE software.  Any direct editing or
     changes made to this file may result in unpredictable
     behavior or data corruption.  It is strongly advised that
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<messages>
<msg type="warning" file="LIT" num="243" delta="unknown" >Logical network <arg fmt="%s" index="1">fifo1/dout&lt;15&gt;</arg> has no load.
</msg>

<msg type="info" file="MapLib" num="562" delta="unknown" >No environment variables are currently set.
</msg>

<msg type="info" file="MapLib" num="986" delta="unknown" >The SAVE constraint for nets has been made more strict starting in 10.1, such that the net driver and load blocks will be preserved as well. To revert to the original behavior please set XIL_MAP_OLD_SAVE.
</msg>

<msg type="info" file="MapLib" num="984" delta="unknown" >SAVE has been detected on the following signal(s):
<arg fmt="%s" index="1">reset,
clk</arg>.
</msg>

<msg type="info" file="LIT" num="244" delta="unknown" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs.
</msg>

</messages>