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<?xml version="1.0" encoding="UTF-8"?><!-- IMPORTANT: This is an internal file that has been generatedby the Xilinx ISE software. Any direct editing orchanges made to this file may result in unpredictablebehavior or data corruption. It is strongly advised thatusers do not edit the contents of this file. --><messages><msg type="warning" file="HDLCompilers" num="259" delta="unknown" ><arg fmt="%s" index="1">"Display_Controller.v" line 49 </arg>Connection to input port '<arg fmt="%s" index="2">din</arg>' does not match port size</msg><msg type="warning" file="Xst" num="2211" delta="unknown" >"<arg fmt="%s" index="1">./fifo_generator_v4_3.v</arg>" line <arg fmt="%d" index="2">48</arg>: Instantiating black box module <<arg fmt="%s" index="3">fifo_generator_v4_3</arg>>.</msg><msg type="warning" file="Xst" num="905" delta="unknown" >"<arg fmt="%s" index="1">color_fsm.v</arg>" line <arg fmt="%d" index="2">52</arg>: One or more signals are missing in the sensitivity list of always block. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:<arg fmt="%s" index="3"><count>, <hcount>, <vcount></arg></msg><msg type="warning" file="Xst" num="647" delta="unknown" >Input <<arg fmt="%s" index="1">pixel_set_rgb<15></arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.</msg><msg type="warning" file="Xst" num="647" delta="unknown" >Input <<arg fmt="%s" index="1">clk_2MHz</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.</msg><msg type="warning" file="Xst" num="737" delta="unknown" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal <<arg fmt="%s" index="2">count</arg>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.</msg><msg type="warning" file="Xst" num="1426" delta="unknown" >The value init of the FF/Latch <arg fmt="%s" index="1">0</arg> hinder the constant cleaning in the block <arg fmt="%s" index="2">count</arg>.You should achieve better results by setting this init to <arg fmt="%i" index="3">1</arg>.</msg><msg type="warning" file="Xst" num="1426" delta="unknown" >The value init of the FF/Latch <arg fmt="%s" index="1">count</arg> hinder the constant cleaning in the block <arg fmt="%s" index="2">color_fsm</arg>.You should achieve better results by setting this init to <arg fmt="%i" index="3">1</arg>.</msg><msg type="info" file="Xst" num="2260" delta="unknown" >The FF/Latch <<arg fmt="%s" index="1">U0/grf.rf/rstblk/wr_rst_reg_1</arg>> in Unit <<arg fmt="%s" index="2">BU2</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><U0/grf.rf/rstblk/wr_rst_reg_0> </arg></msg><msg type="info" file="Xst" num="2260" delta="unknown" >The FF/Latch <<arg fmt="%s" index="1">U0/grf.rf/rstblk/rd_rst_reg_2</arg>> in Unit <<arg fmt="%s" index="2">BU2</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><U0/grf.rf/rstblk/rd_rst_reg_1> <U0/grf.rf/rstblk/rd_rst_reg_0> </arg></msg><msg type="info" file="Xst" num="2260" delta="unknown" >The FF/Latch <<arg fmt="%s" index="1">U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i</arg>> in Unit <<arg fmt="%s" index="2">BU2</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i> </arg></msg><msg type="info" file="Xst" num="2260" delta="unknown" >The FF/Latch <<arg fmt="%s" index="1">U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i</arg>> in Unit <<arg fmt="%s" index="2">BU2</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i> </arg></msg><msg type="info" file="Xst" num="2260" delta="unknown" >The FF/Latch <<arg fmt="%s" index="1">U0/grf.rf/rstblk/wr_rst_reg_1</arg>> in Unit <<arg fmt="%s" index="2">BU2</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><U0/grf.rf/rstblk/wr_rst_reg_0> </arg></msg><msg type="info" file="Xst" num="2260" delta="unknown" >The FF/Latch <<arg fmt="%s" index="1">U0/grf.rf/rstblk/rd_rst_reg_2</arg>> in Unit <<arg fmt="%s" index="2">BU2</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><U0/grf.rf/rstblk/rd_rst_reg_1> <U0/grf.rf/rstblk/rd_rst_reg_0> </arg></msg><msg type="info" file="Xst" num="2260" delta="unknown" >The FF/Latch <<arg fmt="%s" index="1">U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i</arg>> in Unit <<arg fmt="%s" index="2">BU2</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i> </arg></msg><msg type="info" file="Xst" num="2260" delta="unknown" >The FF/Latch <<arg fmt="%s" index="1">U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i</arg>> in Unit <<arg fmt="%s" index="2">BU2</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i> </arg></msg><msg type="info" file="Xst" num="2169" delta="unknown" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.</msg></messages>