Subversion Repositories bu_pacman

##############################################################
#
# Xilinx Core Generator version K.31
# Date: Fri Nov 21 01:30:03 2008
#
##############################################################
#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = False
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = Verilog
SET device = xc3s200
SET devicefamily = spartan3
SET flowvendor = Other
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = ft256
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = True
SET vhdlsim = False
# END Project Options
# BEGIN Select
SELECT Block_Memory_Generator family Xilinx,_Inc. 2.7
# END Select
# BEGIN Parameters
CSET algorithm=Minimum_Area
CSET assume_synchronous_clk=false
CSET byte_size=9
CSET coe_file=//ad/eng/users/n/m/nm2110/workspace/init_mem/mydata.coe
CSET collision_warnings=ALL
CSET component_name=blk_mem_gen_v2_7
CSET disable_collision_warnings=false
CSET disable_out_of_range_warnings=false
CSET ecc=false
CSET enable_a=Use_ENA_Pin
CSET enable_b=Use_ENB_Pin
CSET fill_remaining_memory_locations=false
CSET load_init_file=true
CSET memory_type=True_Dual_Port_RAM
CSET operating_mode_a=WRITE_FIRST
CSET operating_mode_b=WRITE_FIRST
CSET output_reset_value_a=0
CSET output_reset_value_b=0
CSET pipeline_stages=0
CSET primitive=8kx2
CSET read_width_a=16
CSET read_width_b=16
CSET register_porta_output_of_memory_core=false
CSET register_porta_output_of_memory_primitives=false
CSET register_portb_output_of_memory_core=false
CSET register_portb_output_of_memory_primitives=false
CSET remaining_memory_locations=0
CSET single_bit_ecc=false
CSET use_byte_write_enable=false
CSET use_ramb16bwer_reset_behavior=false
CSET use_regcea_pin=false
CSET use_regceb_pin=false
CSET use_ssra_pin=false
CSET use_ssrb_pin=false
CSET write_depth_a=40000
CSET write_width_a=16
CSET write_width_b=16
# END Parameters
GENERATE
# CRC: 99f05bb0