URL
https://opencores.org/ocsvn/bu_pacman/bu_pacman/trunk
Subversion Repositories bu_pacman
[/] [bu_pacman/] [tags/] [arelease/] [templates/] [coregen.xml] - Rev 4
Go to most recent revision | Compare with Previous | Blame | View Log
<?xml version="1.0" encoding="UTF-8"?>
<RootFolder label="COREGEN" treetype="folder" language="COREGEN">
<Folder label="VERILOG Component Instantiation" treetype="folder">
<Template label="blk_mem_gen_v2_7" treetype="template">
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
blk_mem_gen_v2_7 YourInstanceName (
.clka(clka),
.dina(dina), // Bus [15 : 0]
.addra(addra), // Bus [15 : 0]
.ena(ena),
.wea(wea), // Bus [0 : 0]
.douta(douta), // Bus [15 : 0]
.clkb(clkb),
.dinb(dinb), // Bus [15 : 0]
.addrb(addrb), // Bus [15 : 0]
.enb(enb),
.web(web), // Bus [0 : 0]
.doutb(doutb)); // Bus [15 : 0]
</Template>
<Template label="fifo_generator_v4_3" treetype="template">
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
fifo_generator_v4_3 YourInstanceName (
.din(din), // Bus [15 : 0]
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_en(wr_en),
.dout(dout), // Bus [15 : 0]
.empty(empty),
.full(full));
</Template>
</Folder>
<Folder label="VHDL Component Instantiation" treetype="folder">
<Template label="blk_mem_gen_v2_7" treetype="template">
</Template>
<Template label="fifo_generator_v4_3" treetype="template">
</Template>
</Folder>
</RootFolder>
Go to most recent revision | Compare with Previous | Blame | View Log