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[/] [bu_pacman/] [tags/] [arelease/] [test_memory.par] - Rev 7
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Release 10.1 par K.31 (nt)
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
ECE-PHO117-40:: Thu Nov 20 21:07:34 2008
par -w -intstyle ise -ol std -t 1 test_memory_map.ncd test_memory.ncd
test_memory.pcf
Constraints file: test_memory.pcf.
Loading device for application Rf_Device from file '3s200.nph' in environment C:\Xilinx\10.1\ISE.
"test_memory" is an NCD, version 3.2, device xc3s200, package ft256, speed -4
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For
the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". For a
balance between the fastest runtime and best performance, set the effort level to "med".
Device speed data version: "PRODUCTION 1.39 2008-01-09".
Device Utilization Summary:
Number of External IOBs 10 out of 173 5%
Number of LOCed IOBs 10 out of 10 100%
Number of RAMB16s 1 out of 12 8%
Overall effort level (-ol): Standard
Placer effort level (-pl): High
Placer cost table entry (-t): 1
Router effort level (-rl): Standard
WARNING:Par:288 - The signal clk_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal reset_IBUF has no load. PAR will not attempt to route this signal.
Starting Placer
Phase 1.1
Phase 1.1 (Checksum:989695) REAL time: 0 secs
Phase 2.7
Phase 2.7 (Checksum:1312cfe) REAL time: 1 secs
Phase 3.31
Phase 3.31 (Checksum:1c9c37d) REAL time: 1 secs
Phase 4.2
Phase 4.2 (Checksum:26259fc) REAL time: 1 secs
Phase 5.8
............
Phase 5.8 (Checksum:98b7e5) REAL time: 1 secs
Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 1 secs
Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 1 secs
Phase 8.5
Phase 8.5 (Checksum:4c4b3f8) REAL time: 1 secs
REAL time consumed by placer: 1 secs
CPU time consumed by placer: 0 secs
Writing design to file test_memory.ncd
Total REAL time to Placer completion: 1 secs
Total CPU time to Placer completion: 0 secs
Starting Router
Phase 1: 47 unrouted; REAL time: 4 secs
Phase 2: 39 unrouted; REAL time: 4 secs
Phase 3: 0 unrouted; REAL time: 4 secs
Phase 4: 0 unrouted; (0) REAL time: 4 secs
Phase 5: 0 unrouted; (0) REAL time: 4 secs
Phase 6: 0 unrouted; (0) REAL time: 4 secs
Total REAL time to Router completion: 4 secs
Total CPU time to Router completion: 1 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
Timing Score: 0
Generating Pad Report.
All signals are completely routed.
WARNING:Par:283 - There are 2 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 16 secs
Total CPU time to PAR completion: 3 secs
Peak Memory Usage: 100 MB
Placement: Completed - No errors found.
Routing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 4
Number of info messages: 1
Writing design to file test_memory.ncd
PAR done!
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