Subversion Repositories bu_pacman

Release 10.1 - xst K.31 (nt)
Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to X:/Display_Controller/xst/projnav.tmp


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.16 secs
 
--> Parameter xsthdpdir set to X:/Display_Controller/xst


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.16 secs
 
--> Reading design: test_memory.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
     9.1) Device utilization summary
     9.2) Partition Resource Summary
     9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "test_memory.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "test_memory"
Output Format                      : NGC
Target Device                      : xc3s200-4-ft256

---- Source Options
Top Module Name                    : test_memory
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Slice Packing                      : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Yes
Use Synchronous Set                : Yes
Use Synchronous Reset              : Yes
Pack IO Registers into IOBs        : auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Library Search Order               : test_memory.lso
Keep Hierarchy                     : NO
Netlist Hierarchy                  : as_optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
Verilog 2001                       : YES
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "generate_add.v" in library work
Compiling verilog file "clock_divider.v" in library work
Module <generate_add> compiled
Compiling verilog file "blk_mem_gen_v2_7.v" in library work
Module <clk_divider> compiled
Compiling verilog file "test_memory.v" in library work
Module <blk_mem_gen_v2_7> compiled
Module <test_memory> compiled
No errors in compilation
Analysis of file <"test_memory.prj"> succeeded.
 

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for module <test_memory> in library <work>.

Analyzing hierarchy for module <clk_divider> in library <work> with parameters.
        NBIT = "00000000000000000000000000010110"
        NDIV = "00000010111110101111000010000000"

Analyzing hierarchy for module <generate_add> in library <work>.


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <test_memory>.
WARNING:Xst:2211 - "blk_mem_gen_v2_7.v" line 33: Instantiating black box module <blk_mem_gen_v2_7>.
Module <test_memory> is correct for synthesis.
 
Analyzing module <clk_divider> in library <work>.
        NBIT = 32'sb00000000000000000000000000010110
        NDIV = 32'sb00000010111110101111000010000000
Module <clk_divider> is correct for synthesis.
 
Analyzing module <generate_add> in library <work>.
Module <generate_add> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <clk_divider>.
    Related source file is "clock_divider.v".
    Found 22-bit up counter for signal <count>.
    Summary:
        inferred   1 Counter(s).
Unit <clk_divider> synthesized.


Synthesizing Unit <generate_add>.
    Related source file is "generate_add.v".
    Found 16-bit up counter for signal <addr>.
    Summary:
        inferred   1 Counter(s).
Unit <generate_add> synthesized.


Synthesizing Unit <test_memory>.
    Related source file is "test_memory.v".
WARNING:Xst:646 - Signal <frame_1<7:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <doutb> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <test_memory> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                                             : 1
 16-bit up counter                                     : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Loading device for application Rf_Device from file '3s200.nph' in environment C:\Xilinx\10.1\ISE.
Reading core <blk_mem_gen_v2_7.ngc>.
Loading core <blk_mem_gen_v2_7> for timing and area information for instance <mem1>.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Counters                                             : 1
 16-bit up counter                                     : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch <add1/addr_0> (without init value) has a constant value of 0 in block <test_memory>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <add1/addr_1> (without init value) has a constant value of 0 in block <test_memory>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <add1/addr_2> (without init value) has a constant value of 0 in block <test_memory>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <add1/addr_3> (without init value) has a constant value of 0 in block <test_memory>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <add1/addr_4> (without init value) has a constant value of 0 in block <test_memory>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <add1/addr_5> (without init value) has a constant value of 0 in block <test_memory>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <add1/addr_6> (without init value) has a constant value of 0 in block <test_memory>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <add1/addr_7> (without init value) has a constant value of 0 in block <test_memory>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <add1/addr_8> (without init value) has a constant value of 0 in block <test_memory>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <add1/addr_9> (without init value) has a constant value of 0 in block <test_memory>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <add1/addr_10> (without init value) has a constant value of 0 in block <test_memory>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <add1/addr_11> (without init value) has a constant value of 0 in block <test_memory>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <add1/addr_12> (without init value) has a constant value of 0 in block <test_memory>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <add1/addr_13> (without init value) has a constant value of 0 in block <test_memory>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <add1/addr_14> (without init value) has a constant value of 0 in block <test_memory>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <add1/addr_15> (without init value) has a constant value of 0 in block <test_memory>. This FF/Latch will be trimmed during the optimization process.

Optimizing unit <test_memory> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block test_memory, actual ratio is 7.

Final Macro Processing ...

=========================================================================
Final Register Report

Found no macro
=========================================================================

=========================================================================
*                           Partition Report                             *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : test_memory.ngr
Top Level Output File Name         : test_memory
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 10

Cell Usage :
# BELS                             : 439
#      GND                         : 2
#      LUT3                        : 214
#      LUT4                        : 64
#      MUXF5                       : 104
#      MUXF6                       : 36
#      MUXF7                       : 18
#      VCC                         : 1
# FlipFlops/Latches                : 10
#      FDE                         : 10
# RAMS                             : 38
#      RAMB16_S1_S1                : 15
#      RAMB16_S2_S2                : 3
#      RAMB16_S9_S9                : 20
# IO Buffers                       : 8
#      OBUF                        : 8
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200ft256-4 

 Number of Slices:                      144  out of   1920     7%  
 Number of Slice Flip Flops:             10  out of   3840     0%  
 Number of 4 input LUTs:                278  out of   3840     7%  
 Number of IOs:                          10
 Number of bonded IOBs:                   8  out of    173     4%  
 Number of BRAMs:                        38  out of     12   316% (*) 

WARNING:Xst:1336 -  (*) More than 100% of Device resources are used

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+----------------------------------------------------------------------+-------+
Clock Signal                       | Clock buffer(FF name)                                                | Load  |
-----------------------------------+----------------------------------------------------------------------+-------+
N0                                 | NONE(mem1/BU2/U0/blk_mem_generator/valid.cstr/has_mux_a.A/sel_pipe_0)| 30    |
-----------------------------------+----------------------------------------------------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 12.611ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'N0'
  Total number of paths / destination ports: 336 / 8
-------------------------------------------------------------------------
Offset:              12.611ns (Levels of Logic = 7)
  Source:            mem1/BU2/U0/blk_mem_generator/valid.cstr/has_mux_a.A/sel_pipe_0 (FF)
  Destination:       dataout<7> (PAD)
  Source Clock:      N0 rising

  Data Path: mem1/BU2/U0/blk_mem_generator/valid.cstr/has_mux_a.A/sel_pipe_0 to dataout<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q             81   0.720   2.473  U0/blk_mem_generator/valid.cstr/has_mux_a.A/sel_pipe_0 (U0/blk_mem_generator/valid.cstr/has_mux_a.A/sel_pipe<0>)
     LUT3:I0->O            1   0.551   0.000  U0/blk_mem_generator/valid.cstr/has_mux_a.A/Mmux_dout_mux_8 (U0/blk_mem_generator/valid.cstr/has_mux_a.A/Mmux_dout_mux_8)
     MUXF5:I1->O           1   0.360   0.000  U0/blk_mem_generator/valid.cstr/has_mux_a.A/Mmux_dout_mux_7_f5 (U0/blk_mem_generator/valid.cstr/has_mux_a.A/Mmux_dout_mux_7_f5)
     MUXF6:I1->O           1   0.342   0.000  U0/blk_mem_generator/valid.cstr/has_mux_a.A/Mmux_dout_mux_6_f6 (U0/blk_mem_generator/valid.cstr/has_mux_a.A/Mmux_dout_mux_6_f6)
     MUXF7:I1->O           1   0.342   0.827  U0/blk_mem_generator/valid.cstr/has_mux_a.A/Mmux_dout_mux_5_f7 (U0/blk_mem_generator/valid.cstr/has_mux_a.A/Mmux_dout_mux_5_f7)
     LUT4:I3->O            1   0.551   0.801  U0/blk_mem_generator/valid.cstr/has_mux_a.A/sel_pipe<4> (douta(10))
     end scope: 'BU2'
     end scope: 'mem1'
     OBUF:I->O                 5.644          dataout_2_OBUF (dataout<2>)
    ----------------------------------------
    Total                     12.611ns (8.510ns logic, 4.101ns route)
                                       (67.5% logic, 32.5% route)

=========================================================================


Total REAL time to Xst completion: 14.00 secs
Total CPU time to Xst completion: 13.72 secs
 
--> 

Total memory usage is 130992 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   26 (   0 filtered)
Number of infos    :    1 (   0 filtered)