Subversion Repositories bu_pacman

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Release 10.1 Trace  (nt)
Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.

C:\Xilinx\10.1\ISE\bin\nt\unwrapped\trce.exe -ise
X:/Display_Controller/Display_Controller.ise -intstyle ise -e 3 -s 4 -xml
test_memory test_memory.ncd -o test_memory.twr test_memory.pcf -ucf
vga_pins.ucf

Design file:              test_memory.ncd
Physical constraint file: test_memory.pcf
Device,package,speed:     xc3s200,ft256,-4 (PRODUCTION 1.39 2008-01-09)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.



Data Sheet report:
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No constraints were found to generate data for the Data Sheet Report section.
Use the Advanced Analysis (-a) option or generate global constraints for each
clock, its pad to setup and clock to pad paths, and a pad to pad constraint.

Analysis completed Thu Nov 20 21:08:06 2008 
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Trace Settings:
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Trace Settings 

Peak Memory Usage: 69 MB